More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.
configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
This commit is contained in:
Steve Reinhardt
413
src/mem/cache/base_cache.cc
vendored
413
src/mem/cache/base_cache.cc
vendored
@@ -41,18 +41,23 @@
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using namespace std;
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BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
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: Port(_name, _cache), cache(_cache), otherPort(NULL)
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: SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
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blocked(false), waitingOnRetry(false), mustSendRetry(false),
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requestCauses(0)
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{
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blocked = false;
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waitingOnRetry = false;
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}
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BaseCache::BaseCache(const std::string &name, Params ¶ms)
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: MemObject(name),
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blocked(0), blockedSnoop(0),
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mshrQueue(params.numMSHRs, 4),
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writeBuffer(params.numWriteBuffers, params.numMSHRs+1000),
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blkSize(params.blkSize),
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missCount(params.maxMisses), drainEvent(NULL)
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numTarget(params.numTargets),
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blocked(0),
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noTargetMSHR(NULL),
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missCount(params.maxMisses),
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drainEvent(NULL)
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{
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}
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@@ -71,139 +76,21 @@ BaseCache::CachePort::deviceBlockSize()
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return cache->getBlockSize();
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}
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bool
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BaseCache::CachePort::checkFunctional(PacketPtr pkt)
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{
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//Check storage here first
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list<PacketPtr>::iterator i = drainList.begin();
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list<PacketPtr>::iterator iend = drainList.end();
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bool notDone = true;
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while (i != iend && notDone) {
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PacketPtr target = *i;
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// If the target contains data, and it overlaps the
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// probed request, need to update data
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if (target->intersect(pkt)) {
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DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a drain\n",
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pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
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notDone = fixPacket(pkt, target);
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}
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i++;
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}
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//Also check the response not yet ready to be on the list
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std::list<std::pair<Tick,PacketPtr> >::iterator j = transmitList.begin();
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std::list<std::pair<Tick,PacketPtr> >::iterator jend = transmitList.end();
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while (j != jend && notDone) {
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PacketPtr target = j->second;
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// If the target contains data, and it overlaps the
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// probed request, need to update data
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if (target->intersect(pkt)) {
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DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a response\n",
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pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
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notDone = fixDelayedResponsePacket(pkt, target);
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}
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j++;
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}
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return notDone;
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}
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void
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BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
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{
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bool notDone = checkFunctional(pkt);
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if (notDone)
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checkFunctional(pkt);
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if (pkt->result != Packet::Success)
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sendFunctional(pkt);
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}
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void
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BaseCache::CachePort::respond(PacketPtr pkt, Tick time)
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{
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assert(time >= curTick);
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if (pkt->needsResponse()) {
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if (transmitList.empty()) {
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assert(!responseEvent->scheduled());
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responseEvent->schedule(time);
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transmitList.push_back(std::pair<Tick,PacketPtr>(time,pkt));
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return;
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}
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// something is on the list and this belongs at the end
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if (time >= transmitList.back().first) {
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transmitList.push_back(std::pair<Tick,PacketPtr>(time,pkt));
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return;
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}
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// Something is on the list and this belongs somewhere else
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std::list<std::pair<Tick,PacketPtr> >::iterator i =
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transmitList.begin();
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std::list<std::pair<Tick,PacketPtr> >::iterator end =
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transmitList.end();
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bool done = false;
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while (i != end && !done) {
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if (time < i->first) {
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if (i == transmitList.begin()) {
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//Inserting at begining, reschedule
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responseEvent->reschedule(time);
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}
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transmitList.insert(i,std::pair<Tick,PacketPtr>(time,pkt));
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done = true;
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}
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i++;
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}
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}
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else {
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assert(0);
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// this code was on the cpuSidePort only... do we still need it?
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if (pkt->cmd != MemCmd::UpgradeReq)
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{
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delete pkt->req;
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delete pkt;
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}
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}
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}
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bool
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BaseCache::CachePort::drainResponse()
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{
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DPRINTF(CachePort,
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"%s attempting to send a retry for response (%i waiting)\n",
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name(), drainList.size());
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//We have some responses to drain first
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PacketPtr pkt = drainList.front();
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if (sendTiming(pkt)) {
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drainList.pop_front();
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DPRINTF(CachePort, "%s sucessful in sending a retry for"
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"response (%i still waiting)\n", name(), drainList.size());
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if (!drainList.empty() || isBusRequested()) {
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DPRINTF(CachePort, "%s has more responses/requests\n", name());
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return false;
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}
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} else {
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waitingOnRetry = true;
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DPRINTF(CachePort, "%s now waiting on a retry\n", name());
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}
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return true;
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}
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bool
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BaseCache::CachePort::recvRetryCommon()
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{
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assert(waitingOnRetry);
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waitingOnRetry = false;
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if (!drainList.empty()) {
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if (!drainResponse()) {
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// more responses to drain... re-request bus
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scheduleRequestEvent(curTick + 1);
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}
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// Check if we're done draining once this list is empty
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if (drainList.empty()) {
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cache->checkDrain();
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}
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return true;
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}
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return false;
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}
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@@ -451,17 +338,289 @@ BaseCache::regStats()
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.desc("number of cache copies performed")
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;
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writebacks
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.init(maxThreadsPerCPU)
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.name(name() + ".writebacks")
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.desc("number of writebacks")
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.flags(total)
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;
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// MSHR statistics
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// MSHR hit statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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mshr_hits[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_mshr_hits")
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.desc("number of " + cstr + " MSHR hits")
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.flags(total | nozero | nonan)
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;
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}
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demandMshrHits
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.name(name() + ".demand_mshr_hits")
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.desc("number of demand (read+write) MSHR hits")
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.flags(total)
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;
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demandMshrHits = mshr_hits[MemCmd::ReadReq] + mshr_hits[MemCmd::WriteReq];
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overallMshrHits
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.name(name() + ".overall_mshr_hits")
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.desc("number of overall MSHR hits")
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.flags(total)
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;
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overallMshrHits = demandMshrHits + mshr_hits[MemCmd::SoftPFReq] +
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mshr_hits[MemCmd::HardPFReq];
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// MSHR miss statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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mshr_misses[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_mshr_misses")
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.desc("number of " + cstr + " MSHR misses")
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.flags(total | nozero | nonan)
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;
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}
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demandMshrMisses
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.name(name() + ".demand_mshr_misses")
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.desc("number of demand (read+write) MSHR misses")
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.flags(total)
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;
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demandMshrMisses = mshr_misses[MemCmd::ReadReq] + mshr_misses[MemCmd::WriteReq];
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overallMshrMisses
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.name(name() + ".overall_mshr_misses")
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.desc("number of overall MSHR misses")
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.flags(total)
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;
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overallMshrMisses = demandMshrMisses + mshr_misses[MemCmd::SoftPFReq] +
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mshr_misses[MemCmd::HardPFReq];
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// MSHR miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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mshr_miss_latency[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_mshr_miss_latency")
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.desc("number of " + cstr + " MSHR miss cycles")
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.flags(total | nozero | nonan)
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;
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}
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demandMshrMissLatency
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.name(name() + ".demand_mshr_miss_latency")
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.desc("number of demand (read+write) MSHR miss cycles")
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.flags(total)
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;
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demandMshrMissLatency = mshr_miss_latency[MemCmd::ReadReq]
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+ mshr_miss_latency[MemCmd::WriteReq];
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overallMshrMissLatency
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.name(name() + ".overall_mshr_miss_latency")
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.desc("number of overall MSHR miss cycles")
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.flags(total)
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;
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overallMshrMissLatency = demandMshrMissLatency +
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mshr_miss_latency[MemCmd::SoftPFReq] + mshr_miss_latency[MemCmd::HardPFReq];
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// MSHR uncacheable statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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mshr_uncacheable[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_mshr_uncacheable")
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.desc("number of " + cstr + " MSHR uncacheable")
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.flags(total | nozero | nonan)
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;
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}
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overallMshrUncacheable
|
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.name(name() + ".overall_mshr_uncacheable_misses")
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.desc("number of overall MSHR uncacheable misses")
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.flags(total)
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;
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overallMshrUncacheable = mshr_uncacheable[MemCmd::ReadReq]
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+ mshr_uncacheable[MemCmd::WriteReq] + mshr_uncacheable[MemCmd::SoftPFReq]
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+ mshr_uncacheable[MemCmd::HardPFReq];
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|
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// MSHR miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
|
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|
||||
mshr_uncacheable_lat[access_idx]
|
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_mshr_uncacheable_latency")
|
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.desc("number of " + cstr + " MSHR uncacheable cycles")
|
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.flags(total | nozero | nonan)
|
||||
;
|
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}
|
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|
||||
overallMshrUncacheableLatency
|
||||
.name(name() + ".overall_mshr_uncacheable_latency")
|
||||
.desc("number of overall MSHR uncacheable cycles")
|
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.flags(total)
|
||||
;
|
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overallMshrUncacheableLatency = mshr_uncacheable_lat[MemCmd::ReadReq]
|
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+ mshr_uncacheable_lat[MemCmd::WriteReq]
|
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+ mshr_uncacheable_lat[MemCmd::SoftPFReq]
|
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+ mshr_uncacheable_lat[MemCmd::HardPFReq];
|
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|
||||
#if 0
|
||||
// MSHR access formulas
|
||||
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
||||
MemCmd cmd(access_idx);
|
||||
const string &cstr = cmd.toString();
|
||||
|
||||
mshrAccesses[access_idx]
|
||||
.name(name() + "." + cstr + "_mshr_accesses")
|
||||
.desc("number of " + cstr + " mshr accesses(hits+misses)")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
mshrAccesses[access_idx] =
|
||||
mshr_hits[access_idx] + mshr_misses[access_idx]
|
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+ mshr_uncacheable[access_idx];
|
||||
}
|
||||
|
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demandMshrAccesses
|
||||
.name(name() + ".demand_mshr_accesses")
|
||||
.desc("number of demand (read+write) mshr accesses")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
demandMshrAccesses = demandMshrHits + demandMshrMisses;
|
||||
|
||||
overallMshrAccesses
|
||||
.name(name() + ".overall_mshr_accesses")
|
||||
.desc("number of overall (read+write) mshr accesses")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
overallMshrAccesses = overallMshrHits + overallMshrMisses
|
||||
+ overallMshrUncacheable;
|
||||
#endif
|
||||
|
||||
// MSHR miss rate formulas
|
||||
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
||||
MemCmd cmd(access_idx);
|
||||
const string &cstr = cmd.toString();
|
||||
|
||||
mshrMissRate[access_idx]
|
||||
.name(name() + "." + cstr + "_mshr_miss_rate")
|
||||
.desc("mshr miss rate for " + cstr + " accesses")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
|
||||
mshrMissRate[access_idx] =
|
||||
mshr_misses[access_idx] / accesses[access_idx];
|
||||
}
|
||||
|
||||
demandMshrMissRate
|
||||
.name(name() + ".demand_mshr_miss_rate")
|
||||
.desc("mshr miss rate for demand accesses")
|
||||
.flags(total)
|
||||
;
|
||||
demandMshrMissRate = demandMshrMisses / demandAccesses;
|
||||
|
||||
overallMshrMissRate
|
||||
.name(name() + ".overall_mshr_miss_rate")
|
||||
.desc("mshr miss rate for overall accesses")
|
||||
.flags(total)
|
||||
;
|
||||
overallMshrMissRate = overallMshrMisses / overallAccesses;
|
||||
|
||||
// mshrMiss latency formulas
|
||||
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
||||
MemCmd cmd(access_idx);
|
||||
const string &cstr = cmd.toString();
|
||||
|
||||
avgMshrMissLatency[access_idx]
|
||||
.name(name() + "." + cstr + "_avg_mshr_miss_latency")
|
||||
.desc("average " + cstr + " mshr miss latency")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
|
||||
avgMshrMissLatency[access_idx] =
|
||||
mshr_miss_latency[access_idx] / mshr_misses[access_idx];
|
||||
}
|
||||
|
||||
demandAvgMshrMissLatency
|
||||
.name(name() + ".demand_avg_mshr_miss_latency")
|
||||
.desc("average overall mshr miss latency")
|
||||
.flags(total)
|
||||
;
|
||||
demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
|
||||
|
||||
overallAvgMshrMissLatency
|
||||
.name(name() + ".overall_avg_mshr_miss_latency")
|
||||
.desc("average overall mshr miss latency")
|
||||
.flags(total)
|
||||
;
|
||||
overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
|
||||
|
||||
// mshrUncacheable latency formulas
|
||||
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
||||
MemCmd cmd(access_idx);
|
||||
const string &cstr = cmd.toString();
|
||||
|
||||
avgMshrUncacheableLatency[access_idx]
|
||||
.name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
|
||||
.desc("average " + cstr + " mshr uncacheable latency")
|
||||
.flags(total | nozero | nonan)
|
||||
;
|
||||
|
||||
avgMshrUncacheableLatency[access_idx] =
|
||||
mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
|
||||
}
|
||||
|
||||
overallAvgMshrUncacheableLatency
|
||||
.name(name() + ".overall_avg_mshr_uncacheable_latency")
|
||||
.desc("average overall mshr uncacheable latency")
|
||||
.flags(total)
|
||||
;
|
||||
overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
|
||||
|
||||
mshr_cap_events
|
||||
.init(maxThreadsPerCPU)
|
||||
.name(name() + ".mshr_cap_events")
|
||||
.desc("number of times MSHR cap was activated")
|
||||
.flags(total)
|
||||
;
|
||||
|
||||
//software prefetching stats
|
||||
soft_prefetch_mshr_full
|
||||
.init(maxThreadsPerCPU)
|
||||
.name(name() + ".soft_prefetch_mshr_full")
|
||||
.desc("number of mshr full events for SW prefetching instrutions")
|
||||
.flags(total)
|
||||
;
|
||||
|
||||
mshr_no_allocate_misses
|
||||
.name(name() +".no_allocate_misses")
|
||||
.desc("Number of misses that were no-allocate")
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
unsigned int
|
||||
BaseCache::drain(Event *de)
|
||||
{
|
||||
int count = memSidePort->drain(de) + cpuSidePort->drain(de);
|
||||
|
||||
// Set status
|
||||
if (!canDrain()) {
|
||||
if (count != 0) {
|
||||
drainEvent = de;
|
||||
|
||||
changeState(SimObject::Draining);
|
||||
return 1;
|
||||
return count;
|
||||
}
|
||||
|
||||
changeState(SimObject::Drained);
|
||||
|
||||
Reference in New Issue
Block a user