From 35763bdfb2550b74262e040e9cdf9f458ec3ecf4 Mon Sep 17 00:00:00 2001
From: Yang Liu <numbksco@gmail.com>
Date: Tue, 17 Jan 2023 13:57:23 +0800
Subject: [PATCH] arch: Add setRegOperand in VecRegOperand

VecRegOperand also need setRegOperand method to write back execution
result.

Change-Id: Ie50606014827c14a7219558dd003eb4747231649
Co-authored-by: Xuan Hu <huxuan@bosc.ac.cn>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67292
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/isa_parser/operand_types.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 174a54cd4c..113cc2f982 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -372,6 +372,7 @@ class VecRegOperand(RegOperand):
 
     def makeWrite(self):
         return f"""
+        xc->setRegOperand(this, {self.dest_reg_idx}, &tmp_d{self.dest_reg_idx});
         if (traceData) {{
             traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
         }}