diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 174a54cd4c..113cc2f982 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -372,6 +372,7 @@ class VecRegOperand(RegOperand):
 
     def makeWrite(self):
         return f"""
+        xc->setRegOperand(this, {self.dest_reg_idx}, &tmp_d{self.dest_reg_idx});
         if (traceData) {{
             traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
         }}