Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
This commit is contained in:
Nathan Binkert
91
src/mem/cache/BaseCache.py
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91
src/mem/cache/BaseCache.py
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from MemObject import MemObject
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class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
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class BaseCache(MemObject):
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type = 'BaseCache'
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adaptive_compression = Param.Bool(False,
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"Use an adaptive compression scheme")
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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latency = Param.Latency("Latency")
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compressed_bus = Param.Bool(False,
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"This cache connects to a compressed memory")
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compression_latency = Param.Latency('0ns',
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"Latency in cycles of compression algorithm")
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hash_delay = Param.Int(1, "time in cycles of hash access")
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lifo = Param.Bool(False,
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"whether this NIC partition should use LIFO repl. policy")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
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repl = Param.Repl(NULL, "replacement policy")
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size = Param.MemorySize("capacity in bytes")
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split = Param.Bool(False, "whether or not this cache is split")
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split_size = Param.Int(0,
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"How many ways of the cache belong to CPU/LRU partition")
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store_compressed = Param.Bool(False,
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"Store compressed data in the cache")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_miss = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Miss stream")
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prefetch_access = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Access stream")
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prefetcher_size = Param.Int(100,
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"Number of entries in the harware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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"Squash prefetches with a later time on a subsequent miss")
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prefetch_degree = Param.Int(1,
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"Degree of the prefetch depth")
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prefetch_latency = Param.Tick(10,
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"Latency of the prefetcher")
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_cache_check_push = Param.Bool(True,
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"Check if in cash on push or pop of prefetch queue")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to seperate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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cpu_side = Port("Port on side closer to CPU")
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mem_side = Port("Port on side closer to MEM")
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