Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
This commit is contained in:
Nathan Binkert
34
src/dev/BadDevice.py
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34
src/dev/BadDevice.py
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@@ -0,0 +1,34 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
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# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from Device import BasicPioDevice
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class BadDevice(BasicPioDevice):
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type = 'BadDevice'
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devicename = Param.String("Name of device to error on")
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71
src/dev/Device.py
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71
src/dev/Device.py
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@@ -0,0 +1,71 @@
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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class PioDevice(MemObject):
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type = 'PioDevice'
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abstract = True
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pio = Port("Programmed I/O port")
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platform = Param.Platform(Parent.any, "Platform this device is part of")
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system = Param.System(Parent.any, "System this device is part of")
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class BasicPioDevice(PioDevice):
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type = 'BasicPioDevice'
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abstract = True
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pio_addr = Param.Addr("Device Address")
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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class DmaDevice(PioDevice):
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type = 'DmaDevice'
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abstract = True
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dma = Port(Self.pio.peerObj.port, "DMA port")
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min_backoff_delay = Param.Latency('4ns',
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"min time between a nack packet being received and the next request made by the device")
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max_backoff_delay = Param.Latency('10us',
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"max time between a nack packet being received and the next request made by the device")
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class IsaFake(BasicPioDevice):
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type = 'IsaFake'
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pio_size = Param.Addr(0x8, "Size of address range")
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ret_data8 = Param.UInt8(0xFF, "Default data to return")
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ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
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ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
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ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
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ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
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update_data = Param.Bool(False, "Update the data that is returned on writes")
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warn_access = Param.String("", "String to print when device is accessed")
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class BadAddr(IsaFake):
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ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
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44
src/dev/DiskImage.py
Normal file
44
src/dev/DiskImage.py
Normal file
@@ -0,0 +1,44 @@
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from m5.params import *
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class DiskImage(SimObject):
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type = 'DiskImage'
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abstract = True
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image_file = Param.String("disk image file")
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read_only = Param.Bool(False, "read only image")
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class RawDiskImage(DiskImage):
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type = 'RawDiskImage'
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class CowDiskImage(DiskImage):
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type = 'CowDiskImage'
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child = Param.DiskImage(RawDiskImage(read_only=True),
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"child image")
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table_size = Param.Int(65536, "initial table size")
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199
src/dev/Ethernet.py
Normal file
199
src/dev/Ethernet.py
Normal file
@@ -0,0 +1,199 @@
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
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||||
# Authors: Nathan Binkert
|
||||
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||||
from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from Pci import PciDevice, PciConfigData
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class EtherInt(SimObject):
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type = 'EtherInt'
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abstract = True
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peer = Param.EtherInt(NULL, "peer interface")
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class EtherLink(SimObject):
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type = 'EtherLink'
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int1 = Param.EtherInt("interface 1")
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int2 = Param.EtherInt("interface 2")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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class EtherBus(SimObject):
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type = 'EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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class EtherTap(EtherInt):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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class EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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maxlen = Param.Int(96, "max portion of packet data to dump")
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class IGbE(PciDevice):
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type = 'IGbE'
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hardware_address = Param.String("Ethernet Hardware Address")
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use_flow_control = Param.Bool(False,
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"Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
|
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rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
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tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
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rx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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tx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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clock = Param.Clock('500MHz', "Clock speed of the device")
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|
||||
class IGbEPciData(PciConfigData):
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VendorID = 0x8086
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DeviceID = 0x1075
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||||
SubsystemID = 0x1008
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SubsystemVendorID = 0x8086
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Status = 0x0000
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||||
SubClassCode = 0x00
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||||
ClassCode = 0x02
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||||
ProgIF = 0x00
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||||
BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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||||
MaximumLatency = 0x00
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||||
MinimumGrant = 0xff
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '128kB'
|
||||
|
||||
class IGbEInt(EtherInt):
|
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type = 'IGbEInt'
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device = Param.IGbE("Ethernet device of this interface")
|
||||
|
||||
|
||||
|
||||
class EtherDevBase(PciDevice):
|
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
||||
"Ethernet Hardware Address")
|
||||
|
||||
clock = Param.Clock('0ns', "State machine processor frequency")
|
||||
|
||||
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
||||
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
||||
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
|
||||
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
|
||||
|
||||
rx_delay = Param.Latency('1us', "Receive Delay")
|
||||
tx_delay = Param.Latency('1us', "Transmit Delay")
|
||||
rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
|
||||
tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
|
||||
|
||||
rx_filter = Param.Bool(True, "Enable Receive Filter")
|
||||
intr_delay = Param.Latency('10us', "Interrupt propagation delay")
|
||||
rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
|
||||
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
|
||||
rss = Param.Bool(False, "Receive Side Scaling")
|
||||
|
||||
class NSGigEPciData(PciConfigData):
|
||||
VendorID = 0x100B
|
||||
DeviceID = 0x0022
|
||||
Status = 0x0290
|
||||
SubClassCode = 0x00
|
||||
ClassCode = 0x02
|
||||
ProgIF = 0x00
|
||||
BAR0 = 0x00000001
|
||||
BAR1 = 0x00000000
|
||||
BAR2 = 0x00000000
|
||||
BAR3 = 0x00000000
|
||||
BAR4 = 0x00000000
|
||||
BAR5 = 0x00000000
|
||||
MaximumLatency = 0x34
|
||||
MinimumGrant = 0xb0
|
||||
InterruptLine = 0x1e
|
||||
InterruptPin = 0x01
|
||||
BAR0Size = '256B'
|
||||
BAR1Size = '4kB'
|
||||
|
||||
class NSGigE(EtherDevBase):
|
||||
type = 'NSGigE'
|
||||
|
||||
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
||||
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
||||
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
|
||||
|
||||
configdata = NSGigEPciData()
|
||||
|
||||
|
||||
class NSGigEInt(EtherInt):
|
||||
type = 'NSGigEInt'
|
||||
device = Param.NSGigE("Ethernet device of this interface")
|
||||
|
||||
class SinicPciData(PciConfigData):
|
||||
VendorID = 0x1291
|
||||
DeviceID = 0x1293
|
||||
Status = 0x0290
|
||||
SubClassCode = 0x00
|
||||
ClassCode = 0x02
|
||||
ProgIF = 0x00
|
||||
BAR0 = 0x00000000
|
||||
BAR1 = 0x00000000
|
||||
BAR2 = 0x00000000
|
||||
BAR3 = 0x00000000
|
||||
BAR4 = 0x00000000
|
||||
BAR5 = 0x00000000
|
||||
MaximumLatency = 0x34
|
||||
MinimumGrant = 0xb0
|
||||
InterruptLine = 0x1e
|
||||
InterruptPin = 0x01
|
||||
BAR0Size = '64kB'
|
||||
|
||||
class Sinic(EtherDevBase):
|
||||
type = 'Sinic'
|
||||
|
||||
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
|
||||
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
|
||||
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
|
||||
rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
|
||||
rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
|
||||
tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
|
||||
tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
|
||||
virtual_count = Param.UInt32(1, "Virtualized SINIC")
|
||||
zero_copy = Param.Bool(False, "Zero copy receive")
|
||||
delay_copy = Param.Bool(False, "Delayed copy transmit")
|
||||
virtual_addr = Param.Bool(False, "Virtual addressing")
|
||||
|
||||
configdata = SinicPciData()
|
||||
|
||||
class SinicInt(EtherInt):
|
||||
type = 'SinicInt'
|
||||
device = Param.Sinic("Ethernet device of this interface")
|
||||
68
src/dev/Ide.py
Normal file
68
src/dev/Ide.py
Normal file
@@ -0,0 +1,68 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
from Pci import PciDevice, PciConfigData
|
||||
|
||||
class IdeID(Enum): vals = ['master', 'slave']
|
||||
|
||||
class IdeControllerPciData(PciConfigData):
|
||||
VendorID = 0x8086
|
||||
DeviceID = 0x7111
|
||||
Command = 0x0
|
||||
Status = 0x280
|
||||
Revision = 0x0
|
||||
ClassCode = 0x01
|
||||
SubClassCode = 0x01
|
||||
ProgIF = 0x85
|
||||
BAR0 = 0x00000001
|
||||
BAR1 = 0x00000001
|
||||
BAR2 = 0x00000001
|
||||
BAR3 = 0x00000001
|
||||
BAR4 = 0x00000001
|
||||
BAR5 = 0x00000001
|
||||
InterruptLine = 0x1f
|
||||
InterruptPin = 0x01
|
||||
BAR0Size = '8B'
|
||||
BAR1Size = '4B'
|
||||
BAR2Size = '8B'
|
||||
BAR3Size = '4B'
|
||||
BAR4Size = '16B'
|
||||
|
||||
class IdeDisk(SimObject):
|
||||
type = 'IdeDisk'
|
||||
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
|
||||
driveID = Param.IdeID('master', "Drive ID")
|
||||
image = Param.DiskImage("Disk image")
|
||||
|
||||
class IdeController(PciDevice):
|
||||
type = 'IdeController'
|
||||
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
|
||||
|
||||
configdata =IdeControllerPciData()
|
||||
87
src/dev/Pci.py
Normal file
87
src/dev/Pci.py
Normal file
@@ -0,0 +1,87 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
from Device import BasicPioDevice, DmaDevice, PioDevice
|
||||
|
||||
class PciConfigData(SimObject):
|
||||
type = 'PciConfigData'
|
||||
VendorID = Param.UInt16("Vendor ID")
|
||||
DeviceID = Param.UInt16("Device ID")
|
||||
Command = Param.UInt16(0, "Command")
|
||||
Status = Param.UInt16(0, "Status")
|
||||
Revision = Param.UInt8(0, "Device")
|
||||
ProgIF = Param.UInt8(0, "Programming Interface")
|
||||
SubClassCode = Param.UInt8(0, "Sub-Class Code")
|
||||
ClassCode = Param.UInt8(0, "Class Code")
|
||||
CacheLineSize = Param.UInt8(0, "System Cacheline Size")
|
||||
LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
|
||||
HeaderType = Param.UInt8(0, "PCI Header Type")
|
||||
BIST = Param.UInt8(0, "Built In Self Test")
|
||||
|
||||
BAR0 = Param.UInt32(0x00, "Base Address Register 0")
|
||||
BAR1 = Param.UInt32(0x00, "Base Address Register 1")
|
||||
BAR2 = Param.UInt32(0x00, "Base Address Register 2")
|
||||
BAR3 = Param.UInt32(0x00, "Base Address Register 3")
|
||||
BAR4 = Param.UInt32(0x00, "Base Address Register 4")
|
||||
BAR5 = Param.UInt32(0x00, "Base Address Register 5")
|
||||
BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
|
||||
BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
|
||||
BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
|
||||
BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
|
||||
BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
|
||||
BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
|
||||
|
||||
CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
|
||||
SubsystemID = Param.UInt16(0x00, "Subsystem ID")
|
||||
SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
|
||||
ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
|
||||
InterruptLine = Param.UInt8(0x00, "Interrupt Line")
|
||||
InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
|
||||
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
|
||||
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
|
||||
|
||||
class PciConfigAll(PioDevice):
|
||||
type = 'PciConfigAll'
|
||||
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
|
||||
bus = Param.UInt8(0x00, "PCI bus to act as config space for")
|
||||
size = Param.MemorySize32('16MB', "Size of config space")
|
||||
|
||||
|
||||
class PciDevice(DmaDevice):
|
||||
type = 'PciDevice'
|
||||
abstract = True
|
||||
config = Port(Self.pio.peerObj.port, "PCI configuration space port")
|
||||
pci_bus = Param.Int("PCI bus")
|
||||
pci_dev = Param.Int("PCI device number")
|
||||
pci_func = Param.Int("PCI function code")
|
||||
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
|
||||
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
|
||||
config_latency = Param.Latency('20ns', "Config read or write latency")
|
||||
35
src/dev/Platform.py
Normal file
35
src/dev/Platform.py
Normal file
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
class Platform(SimObject):
|
||||
type = 'Platform'
|
||||
abstract = True
|
||||
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
|
||||
@@ -32,6 +32,17 @@
|
||||
Import('*')
|
||||
|
||||
if env['FULL_SYSTEM']:
|
||||
SimObject('BadDevice.py')
|
||||
SimObject('Device.py')
|
||||
SimObject('DiskImage.py')
|
||||
SimObject('Ethernet.py')
|
||||
SimObject('Ide.py')
|
||||
SimObject('Pci.py')
|
||||
SimObject('Platform.py')
|
||||
SimObject('SimConsole.py')
|
||||
SimObject('SimpleDisk.py')
|
||||
SimObject('Uart.py')
|
||||
|
||||
Source('baddev.cc')
|
||||
Source('disk_image.cc')
|
||||
Source('etherbus.cc')
|
||||
|
||||
39
src/dev/SimConsole.py
Normal file
39
src/dev/SimConsole.py
Normal file
@@ -0,0 +1,39 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
|
||||
class SimConsole(SimObject):
|
||||
type = 'SimConsole'
|
||||
append_name = Param.Bool(True, "append name() to filename")
|
||||
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
|
||||
port = Param.TcpPort(3456, "listen port")
|
||||
number = Param.Int(0, "console number")
|
||||
output = Param.String('console', "file to dump output to")
|
||||
35
src/dev/SimpleDisk.py
Normal file
35
src/dev/SimpleDisk.py
Normal file
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
class SimpleDisk(SimObject):
|
||||
type = 'SimpleDisk'
|
||||
disk = Param.DiskImage("Disk Image")
|
||||
system = Param.System(Parent.any, "Sysetm Pointer")
|
||||
45
src/dev/Uart.py
Normal file
45
src/dev/Uart.py
Normal file
@@ -0,0 +1,45 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
from m5 import build_env
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class Uart(BasicPioDevice):
|
||||
type = 'Uart'
|
||||
abstract = True
|
||||
sim_console = Param.SimConsole(Parent.any, "The console")
|
||||
|
||||
class Uart8250(Uart):
|
||||
type = 'Uart8250'
|
||||
|
||||
if build_env['ALPHA_TLASER']:
|
||||
class Uart8530(Uart):
|
||||
type = 'Uart8530'
|
||||
|
||||
38
src/dev/alpha/AlphaConsole.py
Normal file
38
src/dev/alpha/AlphaConsole.py
Normal file
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class AlphaConsole(BasicPioDevice):
|
||||
type = 'AlphaConsole'
|
||||
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
|
||||
disk = Param.SimpleDisk("Simple Disk")
|
||||
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
|
||||
system = Param.AlphaSystem(Parent.any, "system object")
|
||||
@@ -32,6 +32,9 @@
|
||||
Import('*')
|
||||
|
||||
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
|
||||
SimObject('AlphaConsole.py')
|
||||
SimObject('Tsunami.py')
|
||||
|
||||
Source('console.cc')
|
||||
Source('tsunami.cc')
|
||||
Source('tsunami_cchip.cc')
|
||||
|
||||
123
src/dev/alpha/Tsunami.py
Normal file
123
src/dev/alpha/Tsunami.py
Normal file
@@ -0,0 +1,123 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
from Device import BasicPioDevice, IsaFake, BadAddr
|
||||
from Platform import Platform
|
||||
from AlphaConsole import AlphaConsole
|
||||
from Uart import Uart8250
|
||||
from Pci import PciConfigAll
|
||||
from BadDevice import BadDevice
|
||||
|
||||
class TsunamiCChip(BasicPioDevice):
|
||||
type = 'TsunamiCChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
|
||||
class TsunamiIO(BasicPioDevice):
|
||||
type = 'TsunamiIO'
|
||||
time = Param.Time('01/01/2009',
|
||||
"System time to use ('Now' for actual time)")
|
||||
year_is_bcd = Param.Bool(False,
|
||||
"The RTC should interpret the year as a BCD value")
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
|
||||
|
||||
class TsunamiPChip(BasicPioDevice):
|
||||
type = 'TsunamiPChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
|
||||
class Tsunami(Platform):
|
||||
type = 'Tsunami'
|
||||
system = Param.System(Parent.any, "system")
|
||||
|
||||
cchip = TsunamiCChip(pio_addr=0x801a0000000)
|
||||
pchip = TsunamiPChip(pio_addr=0x80180000000)
|
||||
pciconfig = PciConfigAll()
|
||||
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
|
||||
|
||||
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
|
||||
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
|
||||
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
|
||||
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
|
||||
|
||||
fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
|
||||
|
||||
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
|
||||
|
||||
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
|
||||
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
|
||||
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
|
||||
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
|
||||
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
|
||||
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
|
||||
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
|
||||
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
|
||||
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
|
||||
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
|
||||
|
||||
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
|
||||
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
|
||||
|
||||
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
|
||||
io = TsunamiIO(pio_addr=0x801fc000000)
|
||||
uart = Uart8250(pio_addr=0x801fc0003f8)
|
||||
console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
|
||||
|
||||
# Attach I/O devices to specified bus object. Can't do this
|
||||
# earlier, since the bus object itself is typically defined at the
|
||||
# System level.
|
||||
def attachIO(self, bus):
|
||||
self.cchip.pio = bus.port
|
||||
self.pchip.pio = bus.port
|
||||
self.pciconfig.pio = bus.default
|
||||
bus.responder_set = True
|
||||
bus.responder = self.pciconfig
|
||||
self.fake_sm_chip.pio = bus.port
|
||||
self.fake_uart1.pio = bus.port
|
||||
self.fake_uart2.pio = bus.port
|
||||
self.fake_uart3.pio = bus.port
|
||||
self.fake_uart4.pio = bus.port
|
||||
self.fake_ppc.pio = bus.port
|
||||
self.fake_OROM.pio = bus.port
|
||||
self.fake_pnp_addr.pio = bus.port
|
||||
self.fake_pnp_write.pio = bus.port
|
||||
self.fake_pnp_read0.pio = bus.port
|
||||
self.fake_pnp_read1.pio = bus.port
|
||||
self.fake_pnp_read2.pio = bus.port
|
||||
self.fake_pnp_read3.pio = bus.port
|
||||
self.fake_pnp_read4.pio = bus.port
|
||||
self.fake_pnp_read5.pio = bus.port
|
||||
self.fake_pnp_read6.pio = bus.port
|
||||
self.fake_pnp_read7.pio = bus.port
|
||||
self.fake_ata0.pio = bus.port
|
||||
self.fake_ata1.pio = bus.port
|
||||
self.fb.pio = bus.port
|
||||
self.io.pio = bus.port
|
||||
self.uart.pio = bus.port
|
||||
self.console.pio = bus.port
|
||||
@@ -32,6 +32,8 @@
|
||||
Import('*')
|
||||
|
||||
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
|
||||
SimObject('T1000.py')
|
||||
|
||||
Source('dtod.cc')
|
||||
Source('iob.cc')
|
||||
Source('t1000.cc')
|
||||
|
||||
134
src/dev/sparc/T1000.py
Normal file
134
src/dev/sparc/T1000.py
Normal file
@@ -0,0 +1,134 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Gabe Black
|
||||
|
||||
from m5.params import *
|
||||
from m5.proxy import *
|
||||
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
|
||||
from Uart import Uart8250
|
||||
from Platform import Platform
|
||||
from SimConsole import SimConsole
|
||||
|
||||
|
||||
class MmDisk(BasicPioDevice):
|
||||
type = 'MmDisk'
|
||||
image = Param.DiskImage("Disk Image")
|
||||
pio_addr = 0x1F40000000
|
||||
|
||||
class DumbTOD(BasicPioDevice):
|
||||
type = 'DumbTOD'
|
||||
time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
|
||||
pio_addr = 0xfff0c1fff8
|
||||
|
||||
class Iob(PioDevice):
|
||||
type = 'Iob'
|
||||
pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
|
||||
|
||||
|
||||
class T1000(Platform):
|
||||
type = 'T1000'
|
||||
system = Param.System(Parent.any, "system")
|
||||
|
||||
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
|
||||
#warn_access="Accessing Clock Unit -- Unimplemented!")
|
||||
|
||||
fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
|
||||
ret_data64=0x0000000000000000, update_data=False)
|
||||
#warn_access="Accessing Memory Banks -- Unimplemented!")
|
||||
|
||||
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
|
||||
#warn_access="Accessing JBI -- Unimplemented!")
|
||||
|
||||
fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
|
||||
ret_data64=0x0000000000000001, update_data=True)
|
||||
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
|
||||
ret_data64=0x0000000000000001, update_data=True)
|
||||
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
|
||||
ret_data64=0x0000000000000001, update_data=True)
|
||||
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
|
||||
ret_data64=0x0000000000000001, update_data=True)
|
||||
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
|
||||
ret_data64=0x0000000000000000, update_data=True)
|
||||
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
|
||||
ret_data64=0x0000000000000000, update_data=True)
|
||||
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
|
||||
ret_data64=0x0000000000000000, update_data=True)
|
||||
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
|
||||
ret_data64=0x0000000000000000, update_data=True)
|
||||
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
||||
|
||||
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
|
||||
#warn_access="Accessing SSI -- Unimplemented!")
|
||||
|
||||
hconsole = SimConsole()
|
||||
hvuart = Uart8250(pio_addr=0xfff0c2c000)
|
||||
htod = DumbTOD()
|
||||
|
||||
pconsole = SimConsole()
|
||||
puart0 = Uart8250(pio_addr=0x1f10000000)
|
||||
|
||||
iob = Iob()
|
||||
# Attach I/O devices that are on chip
|
||||
def attachOnChipIO(self, bus):
|
||||
self.iob.pio = bus.port
|
||||
self.htod.pio = bus.port
|
||||
|
||||
|
||||
# Attach I/O devices to specified bus object. Can't do this
|
||||
# earlier, since the bus object itself is typically defined at the
|
||||
# System level.
|
||||
def attachIO(self, bus):
|
||||
self.hvuart.sim_console = self.hconsole
|
||||
self.puart0.sim_console = self.pconsole
|
||||
self.fake_clk.pio = bus.port
|
||||
self.fake_membnks.pio = bus.port
|
||||
self.fake_l2_1.pio = bus.port
|
||||
self.fake_l2_2.pio = bus.port
|
||||
self.fake_l2_3.pio = bus.port
|
||||
self.fake_l2_4.pio = bus.port
|
||||
self.fake_l2esr_1.pio = bus.port
|
||||
self.fake_l2esr_2.pio = bus.port
|
||||
self.fake_l2esr_3.pio = bus.port
|
||||
self.fake_l2esr_4.pio = bus.port
|
||||
self.fake_ssi.pio = bus.port
|
||||
self.fake_jbi.pio = bus.port
|
||||
self.puart0.pio = bus.port
|
||||
self.hvuart.pio = bus.port
|
||||
Reference in New Issue
Block a user