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arch: Use const StaticInstPtr references where possible

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This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
This commit is contained in:
Andreas Hansson
2014-09-27 09:08:36 -04:00
parent deb2200671
commit 341dbf2662
47 changed files with 194 additions and 191 deletions
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8
src/cpu/base_dyn_inst.hh
View File

@@ -156,7 +156,7 @@ class BaseDynInst : public ExecContext, public RefCounted
InstSeqNum seqNum;
/** The StaticInst used by this BaseDynInst. */
StaticInstPtr staticInst;
const StaticInstPtr staticInst;
/** Pointer to the Impl's CPU object. */
ImplCPU *cpu;
@@ -204,7 +204,7 @@ class BaseDynInst : public ExecContext, public RefCounted
TheISA::PCState predPC;
/** The Macroop if one exists */
StaticInstPtr macroop;
const StaticInstPtr macroop;
/** How many source registers are ready. */
uint8_t readyRegs;
@@ -427,14 +427,14 @@ class BaseDynInst : public ExecContext, public RefCounted
* @param seq_num The sequence number of the instruction.
* @param cpu Pointer to the instruction's CPU.
*/
BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, ImplCPU *cpu);
/** BaseDynInst constructor given a StaticInst pointer.
* @param _staticInst The StaticInst for this BaseDynInst.
*/
BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
/** BaseDynInst destructor. */
~BaseDynInst();

8
src/cpu/base_dyn_inst_impl.hh
View File

@@ -59,8 +59,8 @@
#include "sim/faults.hh"
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop,
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop,
TheISA::PCState _pc, TheISA::PCState _predPC,
InstSeqNum seq_num, ImplCPU *cpu)
: staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
@@ -74,8 +74,8 @@ BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
}
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop)
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: staticInst(_staticInst), traceData(NULL), macroop(_macroop)
{
seqNum = 0;

2
src/cpu/checker/cpu_impl.hh
View File

@@ -303,7 +303,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
microcodeRom.fetchMicroop(pcState.microPC(), NULL);
} else if (!curMacroStaticInst) {
//We're not in the middle of a macro instruction
StaticInstPtr instPtr = NULL;
StaticInstPtr instPtr = nullptr;
//Predecode, ie bundle up an ExtMachInst
//If more fetch data is needed, pass it in.

2
src/cpu/exetrace.cc
View File

@@ -56,7 +56,7 @@ ExeTracerRecord::dumpTicks(ostream &outs)
}
void
Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
{
ostream &outs = Trace::output();

2
src/cpu/exetrace.hh
View File

@@ -56,7 +56,7 @@ class ExeTracerRecord : public InstRecord
{
}
void traceInst(StaticInstPtr inst, bool ran);
void traceInst(const StaticInstPtr &inst, bool ran);
void dump();
virtual void dumpTicks(std::ostream &outs);

2
src/cpu/minor/func_unit.cc
View File

@@ -199,7 +199,7 @@ FUPipeline::advance()
}
MinorFUTiming *
FUPipeline::findTiming(StaticInstPtr inst)
FUPipeline::findTiming(const StaticInstPtr &inst)
{
#if THE_ISA == ARM_ISA
/* This should work for any ISA with a POD mach_inst */

2
src/cpu/minor/func_unit.hh
View File

@@ -257,7 +257,7 @@ class FUPipeline : public FUPipelineBase, public FuncUnit
/** Find the extra timing information for this instruction. Returns
* NULL if no decode info. is found */
MinorFUTiming *findTiming(StaticInstPtr inst);
MinorFUTiming *findTiming(const StaticInstPtr &inst);
/** Step the pipeline. Allow multiple steps? */
void advance();

5
src/cpu/o3/cpu.cc
View File

@@ -946,12 +946,13 @@ FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
this->interrupts->updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->trap(interrupt, 0, NULL);
this->trap(interrupt, 0, nullptr);
}
template <class Impl>
void
FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst)
FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
const StaticInstPtr &inst)
{
// Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid], inst);

2
src/cpu/o3/cpu.hh
View File

@@ -376,7 +376,7 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);

5
src/cpu/o3/dyn_inst.hh
View File

@@ -83,12 +83,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop);
BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop);
~BaseO3DynInst();

8
src/cpu/o3/dyn_inst_impl.hh
View File

@@ -49,8 +49,8 @@
#include "debug/O3PipeView.hh"
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
StaticInstPtr macroop,
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu)
: BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
@@ -59,8 +59,8 @@ BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
}
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
StaticInstPtr _macroop)
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: BaseDynInst<Impl>(_staticInst, _macroop)
{
initVars();

4
src/cpu/pred/bpred_unit.hh
View File

@@ -87,9 +87,9 @@ class BPredUnit : public SimObject
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
bool predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
TheISA::PCState &pc, ThreadID tid);
bool predictInOrder(StaticInstPtr &inst, const InstSeqNum &seqNum,
bool predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum,
int asid, TheISA::PCState &instPC,
TheISA::PCState &predPC, ThreadID tid);

4
src/cpu/pred/bpred_unit_impl.hh
View File

@@ -129,7 +129,7 @@ BPredUnit::drainSanityCheck() const
}
bool
BPredUnit::predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
TheISA::PCState &pc, ThreadID tid)
{
// See if branch predictor predicts taken.
@@ -244,7 +244,7 @@ BPredUnit::predict(StaticInstPtr &inst, const InstSeqNum &seqNum,
}
bool
BPredUnit::predictInOrder(StaticInstPtr &inst, const InstSeqNum &seqNum,
BPredUnit::predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum,
int asid, TheISA::PCState &instPC,
TheISA::PCState &predPC, ThreadID tid)
{

4
src/cpu/profile.hh
View File

@@ -73,7 +73,7 @@ class FunctionProfile
FunctionProfile(const SymbolTable *symtab);
~FunctionProfile();
ProfileNode *consume(ThreadContext *tc, StaticInstPtr inst);
ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst);
ProfileNode *consume(const std::vector<Addr> &stack);
void clear();
void dump(ThreadContext *tc, std::ostream &out) const;
@@ -81,7 +81,7 @@ class FunctionProfile
};
inline ProfileNode *
FunctionProfile::consume(ThreadContext *tc, StaticInstPtr inst)
FunctionProfile::consume(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!trace.trace(tc, inst))
return NULL;

2
src/cpu/simple/probes/simpoint.cc
View File

@@ -77,7 +77,7 @@ void
SimPoint::profile(const std::pair<SimpleThread*, StaticInstPtr>& p)
{
SimpleThread* thread = p.first;
StaticInstPtr inst = p.second;
const StaticInstPtr &inst = p.second;
if (!currentBBVInstCount)
currentBBV.first = thread->pcState().instAddr();

2
src/cpu/timing_expr.cc
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@@ -40,7 +40,7 @@
#include "base/intmath.hh"
#include "cpu/timing_expr.hh"
TimingExprEvalContext::TimingExprEvalContext (StaticInstPtr inst_,
TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_,
ThreadContext *thread_,
TimingExprLet *let_) :
inst(inst_), thread(thread_), let(let_)

4
src/cpu/timing_expr.hh
View File

@@ -73,7 +73,7 @@ class TimingExprEvalContext
{
public:
/** Special visible context */
StaticInstPtr inst;
const StaticInstPtr &inst;
ThreadContext *thread;
/** Context visible as sub expressions. results will hold the results
@@ -83,7 +83,7 @@ class TimingExprEvalContext
std::vector<uint64_t> results;
std::vector<bool > resultAvailable;
TimingExprEvalContext(StaticInstPtr inst_,
TimingExprEvalContext(const StaticInstPtr &inst_,
ThreadContext *thread_, TimingExprLet *let_);
};