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mem: HBMCtrl changes to allow PC data buses to be in different states

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This change updates the HBMCtrl such that both pseudo channels
can be in separate states (read or write) at the same time. In
addition, the controller queues are now always split in two
halves for both pseudo channels.

Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
2022-11-10 13:26:44 -08:00
parent 65d077d795
commit 32df25e426
12 changed files with 122 additions and 116 deletions
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8
src/mem/nvm_interface.cc
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@@ -402,9 +402,9 @@ NVMInterface::processReadReadyEvent()
bool
NVMInterface::burstReady(MemPacket* pkt) const {
bool read_rdy = pkt->isRead() && (ctrl->inReadBusState(true)) &&
(pkt->readyTime <= curTick()) && (numReadDataReady > 0);
bool write_rdy = !pkt->isRead() && !ctrl->inReadBusState(true) &&
bool read_rdy = pkt->isRead() && (ctrl->inReadBusState(true, this)) &&
(pkt->readyTime <= curTick()) && (numReadDataReady > 0);
bool write_rdy = !pkt->isRead() && !ctrl->inReadBusState(true, this) &&
!writeRespQueueFull();
return (read_rdy || write_rdy);
}
@@ -613,7 +613,7 @@ NVMInterface::isBusy(bool read_queue_empty, bool all_writes_nvm)
// Only assert busy for the write case when there are also
// no reads in Q and the write queue only contains NVM commands
// This allows the bus state to switch and service reads
return (ctrl->inReadBusState(true) ?
return (ctrl->inReadBusState(true, this) ?
(numReadDataReady == 0) && !read_queue_empty :
writeRespQueueFull() && read_queue_empty &&
all_writes_nvm);