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mem: HBMCtrl changes to allow PC data buses to be in different states

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This change updates the HBMCtrl such that both pseudo channels
can be in separate states (read or write) at the same time. In
addition, the controller queues are now always split in two
halves for both pseudo channels.

Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
2022-11-10 13:26:44 -08:00
parent 65d077d795
commit 32df25e426
12 changed files with 122 additions and 116 deletions
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20
src/mem/dram_interface.cc
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@@ -1068,13 +1068,14 @@ DRAMInterface::minBankPrep(const MemPacketQueue& queue,
// latest Tick for which ACT can occur without
// incurring additoinal delay on the data bus
const Tick tRCD = ctrl->inReadBusState(false) ?
tRCD_RD : tRCD_WR;
const Tick tRCD = ctrl->inReadBusState(false, this) ?
tRCD_RD : tRCD_WR;
const Tick hidden_act_max =
std::max(min_col_at - tRCD, curTick());
// When is the earliest the R/W burst can issue?
const Tick col_allowed_at = ctrl->inReadBusState(false) ?
const Tick col_allowed_at = ctrl->inReadBusState(false,
this) ?
ranks[i]->banks[j].rdAllowedAt :
ranks[i]->banks[j].wrAllowedAt;
Tick col_at = std::max(col_allowed_at, act_at + tRCD);
@@ -1180,10 +1181,10 @@ bool
DRAMInterface::Rank::isQueueEmpty() const
{
// check commmands in Q based on current bus direction
bool no_queued_cmds = (dram.ctrl->inReadBusState(true) &&
(readEntries == 0))
|| (dram.ctrl->inWriteBusState(true) &&
(writeEntries == 0));
bool no_queued_cmds = (dram.ctrl->inReadBusState(true, &(this->dram))
&& (readEntries == 0)) ||
(dram.ctrl->inWriteBusState(true, &(this->dram))
&& (writeEntries == 0));
return no_queued_cmds;
}
@@ -1669,7 +1670,7 @@ DRAMInterface::Rank::processPowerEvent()
// completed refresh event, ensure next request is scheduled
if (!(dram.ctrl->requestEventScheduled(dram.pseudoChannel))) {
DPRINTF(DRAM, "Scheduling next request after refreshing"
" rank %d\n", rank);
" rank %d, PC %d \n", rank, dram.pseudoChannel);
dram.ctrl->restartScheduler(curTick(), dram.pseudoChannel);
}
}
@@ -1831,7 +1832,8 @@ DRAMInterface::Rank::resetStats() {
bool
DRAMInterface::Rank::forceSelfRefreshExit() const {
return (readEntries != 0) ||
(dram.ctrl->inWriteBusState(true) && (writeEntries != 0));
(dram.ctrl->inWriteBusState(true, &(this->dram))
&& (writeEntries != 0));
}
void