From 32db3b4042a552b98680d81f1703d53a6a3d8a5a Mon Sep 17 00:00:00 2001
From: Yu-hsin Wang <yuhsingw@google.com>
Date: Fri, 30 Jul 2021 09:56:25 +0800
Subject: [PATCH] fastmodel: add memory space id map and getter

Change-Id: Ia9bd467b72ed59ba2b3d2aaf402761779c4e76e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48867
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/fastmodel/iris/thread_context.cc | 12 ++++++++++++
 src/arch/arm/fastmodel/iris/thread_context.hh |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index 87e4e77464..0d2f0b3dbb 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -45,6 +45,7 @@
 #include <vector>
 
 #include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/fastmodel/iris/memory_spaces.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/utility.hh"
 #include "base/logging.hh"
@@ -70,6 +71,10 @@ ThreadContext::initFromIrisInstance(const ResourceMap &resources)
     suspend();
 
     call().memory_getMemorySpaces(_instId, memorySpaces);
+    for (const auto &space: memorySpaces) {
+        memorySpaceIds.emplace(
+            Iris::CanonicalMsn(space.canonicalMsn), space.spaceId);
+    }
     call().memory_getUsefulAddressTranslations(_instId, translations);
 
     typedef ThreadContext Self;
@@ -120,6 +125,13 @@ ThreadContext::extractResourceMap(
     }
 }
 
+iris::MemorySpaceId
+ThreadContext::getMemorySpaceId(const Iris::CanonicalMsn& msn) const
+{
+    auto it = memorySpaceIds.find(msn);
+    return it == memorySpaceIds.end() ? iris::IRIS_UINT64_MAX : it->second;
+}
+
 void
 ThreadContext::maintainStepping()
 {
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index d16b480479..ddc08eb169 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,7 +31,9 @@
 #include <list>
 #include <map>
 #include <memory>
+#include <unordered_map>
 
+#include "arch/arm/fastmodel/iris/memory_spaces.hh"
 #include "arch/arm/regs/vec.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -56,6 +58,9 @@ class ThreadContext : public gem5::ThreadContext
     typedef std::vector<iris::ResourceId> ResourceIds;
     typedef std::map<int, std::string> IdxNameMap;
 
+    typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId>
+        MemorySpaceMap;
+
   protected:
     gem5::BaseCPU *_cpu;
     int _threadId;
@@ -81,6 +86,7 @@ class ThreadContext : public gem5::ThreadContext
             const ResourceMap &resources, const std::string &name);
     void extractResourceMap(ResourceIds &ids,
             const ResourceMap &resources, const IdxNameMap &idx_names);
+    iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn& msn) const;
 
 
     ResourceIds miscRegIds;
@@ -97,6 +103,7 @@ class ThreadContext : public gem5::ThreadContext
 
     std::vector<iris::MemorySpaceInfo> memorySpaces;
     std::vector<iris::MemorySupportedAddressTranslationResult> translations;
+    MemorySpaceMap memorySpaceIds;
 
     // A queue to keep track of instruction count based events.
     EventQueue comInstEventQueue;