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Fixes to get ALPHA_FS and ALPHA_SE to compile again.

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--HG--
extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
This commit is contained in:
Gabe Black
2006-12-20 20:44:06 -05:00
parent f13155393d
commit 327f451eb7
5 changed files with 22 additions and 11 deletions
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5
src/cpu/o3/alpha/dyn_inst.hh
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@@ -73,8 +73,9 @@ class AlphaDynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
O3CPU *cpu);
AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
Addr Pred_PC, Addr Pred_NPC,
InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
AlphaDynInst(StaticInstPtr &_staticInst);

5
src/cpu/o3/alpha/dyn_inst_impl.hh
View File

@@ -31,9 +31,10 @@
#include "cpu/o3/alpha/dyn_inst.hh"
template <class Impl>
AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
Addr Pred_PC, Addr Pred_NPC,
InstSeqNum seq_num, O3CPU *cpu)
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
: BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu)
{
initVars();
}

7
src/cpu/o3/fetch_impl.hh
View File

@@ -1256,10 +1256,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
ext_inst = TheISA::NoopMachInst;
// Create a new DynInst from the dummy nop.
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
next_PC,
DynInstPtr instruction = new DynInst(ext_inst,
fetch_PC, fetch_NPC,
next_PC, next_NPC,
inst_seq, cpu);
instruction->setPredTarg(next_PC + instSize);
instruction->setPredTarg(next_PC, next_NPC);
instruction->setTid(tid);
instruction->setASID(tid);