stats: Update stats to match cache changes
This commit is contained in:
Andreas Hansson
@@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu
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sim_ticks 1869358498000 # Number of ticks simulated
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final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2397277 # Simulator instruction rate (inst/s)
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host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 68943602925 # Simulator tick rate (ticks/s)
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host_mem_usage 377676 # Number of bytes of host memory used
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host_seconds 27.11 # Real time elapsed on the host
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host_inst_rate 2198730 # Simulator instruction rate (inst/s)
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host_op_rate 2198729 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 63233555824 # Simulator tick rate (ticks/s)
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host_mem_usage 377528 # Number of bytes of host memory used
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host_seconds 29.56 # Real time elapsed on the host
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sim_insts 65000470 # Number of instructions simulated
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sim_ops 65000470 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory
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system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s)
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system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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@@ -86,61 +86,6 @@ system.cpu0.itb.data_accesses 0 # DT
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system.cpu0.numCycles 3738723791 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 49478313 # Number of instructions committed
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system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
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system.cpu0.num_func_calls 1124639 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 46202260 # number of integer instructions
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system.cpu0.num_fp_insts 197598 # number of float instructions
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system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
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system.cpu0.num_mem_refs 12536155 # number of memory refs
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system.cpu0.num_load_insts 7783785 # Number of load instructions
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system.cpu0.num_store_insts 4752370 # Number of store instructions
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system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles
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system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles
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system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
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system.cpu0.Branches 7530941 # Number of branches fetched
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system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction
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system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction
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system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
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system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction
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system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction
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system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction
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system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::total 49486454 # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
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system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed
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@@ -231,6 +176,61 @@ system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # n
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system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
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system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
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system.cpu0.committedInsts 49478313 # Number of instructions committed
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system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
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system.cpu0.num_func_calls 1124639 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 46202260 # number of integer instructions
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system.cpu0.num_fp_insts 197598 # number of float instructions
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system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
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system.cpu0.num_mem_refs 12536155 # number of memory refs
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system.cpu0.num_load_insts 7783785 # Number of load instructions
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system.cpu0.num_store_insts 4752370 # Number of store instructions
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system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles
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system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles
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system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
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system.cpu0.Branches 7530941 # Number of branches fetched
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system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction
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system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction
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system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
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system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction
|
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system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction
|
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system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
|
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system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
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||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
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system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction
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||||
system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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||||
system.cpu0.op_class::total 49486454 # Class of executed instruction
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||||
system.cpu0.dcache.tags.replacements 1781373 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use
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system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks.
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@@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks
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||||
system.cpu0.dcache.writebacks::total 632989 # number of writebacks
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||||
system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks
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system.cpu0.dcache.writebacks::total 632988 # number of writebacks
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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||||
system.cpu0.icache.tags.replacements 618298 # number of replacements
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system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use
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@@ -354,6 +354,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks
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system.cpu0.icache.writebacks::total 618298 # number of writebacks
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||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
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system.cpu1.dtb.fetch_misses 0 # ITB misses
|
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@@ -390,61 +392,6 @@ system.cpu1.itb.data_accesses 0 # DT
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system.cpu1.numCycles 3738297607 # number of cpu cycles simulated
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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||||
system.cpu1.committedInsts 15522157 # Number of instructions committed
|
||||
system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 493140 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 14295542 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 198941 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 4961785 # number of memory refs
|
||||
system.cpu1.num_load_insts 2849089 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2112696 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
|
||||
system.cpu1.Branches 2214162 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 15525873 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed
|
||||
@@ -518,6 +465,61 @@ system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # nu
|
||||
system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
|
||||
system.cpu1.committedInsts 15522157 # Number of instructions committed
|
||||
system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 493140 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 14295542 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 198941 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 4961785 # number of memory refs
|
||||
system.cpu1.num_load_insts 2849089 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2112696 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
|
||||
system.cpu1.Branches 2214162 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 15525873 # Class of executed instruction
|
||||
system.cpu1.dcache.tags.replacements 201756 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks.
|
||||
@@ -639,6 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 380671 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
@@ -737,22 +741,22 @@ system.iocache.cache_copies 0 # nu
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 999687 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 999918 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id
|
||||
@@ -761,62 +765,66 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 #
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 46365678 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46365678 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 777520 # number of Writeback hits
|
||||
system.l2c.tags.tag_accesses 46365909 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46365909 # Number of data accesses
|
||||
system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738161 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910319 # number of overall hits
|
||||
system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738156 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185614 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910402 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12102 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066180 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12104 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066097 # number of overall misses
|
||||
system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses)
|
||||
@@ -848,25 +856,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.882002 # mi
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -875,47 +883,47 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 80913 # number of writebacks
|
||||
system.l2c.writebacks::total 80913 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 80921 # number of writebacks
|
||||
system.l2c.writebacks::total 80921 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948866 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948782 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 122433 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917961 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917844 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 126472 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124247 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 126447 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124222 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2205834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2205642 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2205834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2205642 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
@@ -926,8 +934,9 @@ system.toL2Bus.trans_dist::ReadReq 7449 # Tr
|
||||
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution
|
||||
@@ -940,17 +949,17 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1083281 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1083512 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
|
||||
@@ -958,7 +967,7 @@ system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
||||
@@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu
|
||||
sim_ticks 1829332273500 # Number of ticks simulated
|
||||
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2390951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72850763127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 374092 # Number of bytes of host memory used
|
||||
host_seconds 25.11 # Real time elapsed on the host
|
||||
host_inst_rate 2238603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2238602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68208828665 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 373932 # Number of bytes of host memory used
|
||||
host_seconds 26.82 # Real time elapsed on the host
|
||||
sim_insts 60038341 # Number of instructions simulated
|
||||
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -76,61 +76,6 @@ system.cpu.itb.data_accesses 0 # DT
|
||||
system.cpu.numCycles 3658670905 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064400 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
@@ -216,6 +161,61 @@ system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # nu
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064400 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2042728 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks.
|
||||
@@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833493 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833492 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 919605 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use
|
||||
@@ -335,19 +335,21 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 919605 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919605 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992219 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 992425 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||
@@ -356,40 +358,44 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses)
|
||||
@@ -408,16 +414,16 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -426,8 +432,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74365 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -439,8 +445,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Tr
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution
|
||||
@@ -450,21 +457,21 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075788 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075994 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
@@ -563,42 +570,42 @@ system.iocache.writebacks::writebacks 41512 # nu
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948374 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 115846 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917156 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917027 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2150005 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2149824 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2150005 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2149824 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1159279 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22604281025 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628452 # Number of bytes of host memory used
|
||||
host_seconds 123.16 # Real time elapsed on the host
|
||||
host_inst_rate 1280554 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1558869 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24968967598 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628580 # Number of bytes of host memory used
|
||||
host_seconds 111.49 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT
|
||||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
@@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
@@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
@@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
@@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
@@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
@@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
@@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1171566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22843865684 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624228 # Number of bytes of host memory used
|
||||
host_seconds 121.87 # Real time elapsed on the host
|
||||
host_inst_rate 1269873 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1545867 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24760705808 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624348 # Number of bytes of host memory used
|
||||
host_seconds 112.43 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT
|
||||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
@@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
@@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
@@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
@@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
@@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
@@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
@@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1174884 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22908545755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623708 # Number of bytes of host memory used
|
||||
host_seconds 121.52 # Real time elapsed on the host
|
||||
host_inst_rate 1268879 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1544656 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24741311872 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623824 # Number of bytes of host memory used
|
||||
host_seconds 112.52 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -226,6 +226,8 @@ system.cpu0.itb.accesses 74781709 # DT
|
||||
system.cpu0.numCycles 5536444792 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu0.committedInsts 72626333 # Number of instructions committed
|
||||
system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses
|
||||
@@ -283,8 +285,6 @@ system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Cl
|
||||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 89742700 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu0.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks.
|
||||
@@ -459,6 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
@@ -599,6 +601,8 @@ system.cpu1.itb.accesses 72262399 # DT
|
||||
system.cpu1.numCycles 88040649 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.committedInsts 70146546 # Number of instructions committed
|
||||
system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses
|
||||
@@ -656,8 +660,6 @@ system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Cl
|
||||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 87477212 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
@@ -801,8 +803,10 @@ system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # nu
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 682264 # number of Writeback hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
@@ -872,8 +876,10 @@ system.l2c.ReadReq_accesses::cpu0.itb.walker 2288
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
@@ -955,7 +961,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
||||
system.membus.trans_dist::ReadResp 74196 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138133 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
@@ -1044,8 +1050,9 @@ system.toL2Bus.trans_dist::ReadReq 71244 # Tr
|
||||
system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
@@ -1058,11 +1065,11 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 182968 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,55 +4,57 @@ sim_seconds 5.112152 # Nu
|
||||
sim_ticks 5112152301500 # Number of ticks simulated
|
||||
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1349307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34477807791 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659588 # Number of bytes of host memory used
|
||||
host_seconds 148.27 # Real time elapsed on the host
|
||||
host_inst_rate 1265336 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2590419 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32332152611 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659496 # Number of bytes of host memory used
|
||||
host_seconds 158.11 # Real time elapsed on the host
|
||||
sim_insts 200066731 # Number of instructions simulated
|
||||
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 853568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10615616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11497920 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 853568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 853568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9269440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9269440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13337 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165869 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 179655 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144835 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144835 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166968 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2076545 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2249135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166968 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166968 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813217 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813217 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813217 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 166968 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4062352 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224308568 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 200066731 # Number of instructions committed
|
||||
system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses
|
||||
@@ -110,8 +112,6 @@ system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Cl
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409581402 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 1621902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks.
|
||||
@@ -279,6 +279,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 792216 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792216 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use
|
||||
@@ -335,22 +337,22 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 106193 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 106204 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2531.452775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.791178 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038627 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159327 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
@@ -359,52 +361,56 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179780 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179780 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779384 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779384 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275199 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284751 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779384 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454979 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2243915 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779384 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454979 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2243915 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134641 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134641 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13338 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13338 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32163 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 32169 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13338 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166804 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180148 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13338 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166804 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180148 # number of overall misses
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538777 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538777 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180051 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses)
|
||||
@@ -427,24 +433,24 @@ system.cpu.l2cache.overall_accesses::cpu.data 1621783
|
||||
system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428219 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428219 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016826 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016826 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024601 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024427 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016826 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102852 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074317 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016826 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102852 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074317 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -453,8 +459,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98168 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98177 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -466,8 +472,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Tr
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution
|
||||
@@ -479,17 +486,17 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203459 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203470 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
|
||||
@@ -497,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||
@@ -602,16 +609,16 @@ system.iocache.writebacks::writebacks 46667 # nu
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903747 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 144835 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8392 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134360 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134355 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46410 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8271 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution
|
||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
|
||||
@@ -620,32 +627,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17793920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43218681 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 14256770 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 14256561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256770 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256561 # Request fanout histogram
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
||||
sim_ticks 21900500 # Number of ticks simulated
|
||||
final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 94413 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 94393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 324370159 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297000 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 101932 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101910 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 350189482 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296592 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32545500 # Number of ticks simulated
|
||||
final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000036 # Number of seconds simulated
|
||||
sim_ticks 35667500 # Number of ticks simulated
|
||||
final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 507828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 507304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2581337246 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294696 # Number of bytes of host memory used
|
||||
host_inst_rate 607241 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 606492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3381446720 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294520 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
||||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 65091 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 71335 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
@@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu
|
||||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 65091 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 71335 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
@@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
|
||||
@@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
|
||||
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
@@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031
|
||||
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
||||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
@@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
|
||||
@@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n
|
||||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
@@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587
|
||||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279
|
||||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
|
||||
@@ -344,18 +344,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -380,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -412,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -436,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -479,11 +479,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
@@ -504,8 +504,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000012 # Nu
|
||||
sim_ticks 12363500 # Number of ticks simulated
|
||||
final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79707 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 412680664 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295680 # Number of bytes of host memory used
|
||||
host_inst_rate 83593 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 432562452 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295260 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16524500 # Number of ticks simulated
|
||||
final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18239500 # Number of ticks simulated
|
||||
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 315037 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 314537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2013954906 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293376 # Number of bytes of host memory used
|
||||
host_inst_rate 407753 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 406852 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2874172707 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293212 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu
|
||||
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 33049 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 36479 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
@@ -82,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 33049 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 36479 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
@@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
|
||||
@@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n
|
||||
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 82 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
@@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656
|
||||
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82
|
||||
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
@@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
|
||||
@@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n
|
||||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
@@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032
|
||||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163
|
||||
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
|
||||
@@ -338,18 +338,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -374,18 +374,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -406,18 +406,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -430,18 +430,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -475,7 +475,7 @@ system.cpu.toL2Bus.snoop_fanout::total 245 # Re
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
@@ -498,8 +498,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 245 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.7 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000030 # Nu
|
||||
sim_ticks 29949500 # Number of ticks simulated
|
||||
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110305 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 129095 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 716958322 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313816 # Number of bytes of host memory used
|
||||
host_inst_rate 117235 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 137200 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 761957462 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313960 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
@@ -567,6 +567,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
|
||||
@@ -609,6 +611,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
|
||||
@@ -643,6 +647,8 @@ system.cpu.l2cache.demand_miss_latency::total 31692000
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -749,7 +755,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
|
||||
@@ -757,22 +763,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 103
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
||||
sim_ticks 17170000 # Number of ticks simulated
|
||||
final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50361 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188251031 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313812 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 54905 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64292 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 205230571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313448 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -979,6 +979,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits
|
||||
@@ -1178,18 +1180,18 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25848500 # Number of ticks simulated
|
||||
final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28298500 # Number of ticks simulated
|
||||
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 341128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 397821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1927554064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312280 # Number of bytes of host memory used
|
||||
host_inst_rate 321731 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 375194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1990329160 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311896 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
||||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
@@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 51697 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 56597 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4566 # Number of instructions committed
|
||||
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu
|
||||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1008 # Number of branches fetched
|
||||
@@ -208,17 +208,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
|
||||
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n
|
||||
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 141 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
@@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
|
||||
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
@@ -310,27 +310,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
|
||||
@@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
||||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
|
||||
@@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323
|
||||
system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -378,45 +378,47 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
|
||||
@@ -442,18 +444,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -478,18 +480,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -510,18 +512,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -534,18 +536,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -565,23 +567,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
@@ -602,8 +604,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 350 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
sim_ticks 22451000 # Number of ticks simulated
|
||||
final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 22454000 # Number of ticks simulated
|
||||
final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76622 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 344943613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294148 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 82798 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 82780 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 372464129 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294232 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 4986 # Number of instructions simulated
|
||||
sim_ops 4986 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20992 # Nu
|
||||
system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 22364000 # Total gap between requests
|
||||
system.physmem.totGap 22367000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
@@ -206,9 +206,9 @@ system.physmem.totBusLat 2345000 # To
|
||||
system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.44 # Data bus utilization in percentage
|
||||
@@ -220,7 +220,7 @@ system.physmem.readRowHits 355 # Nu
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 47684.43 # Average gap between requests
|
||||
system.physmem.avgGap 47690.83 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
@@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 44903 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 44909 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
|
||||
@@ -308,8 +308,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
|
||||
@@ -436,7 +436,7 @@ system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Ty
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
|
||||
system.cpu.iq.rate 0.176759 # Inst issue rate
|
||||
system.cpu.iq.rate 0.176735 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
|
||||
@@ -480,13 +480,13 @@ system.cpu.iew.exec_nop 1483 # nu
|
||||
system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1353 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1053 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.170835 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.170812 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2832 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
|
||||
@@ -558,27 +558,27 @@ system.cpu.commit.bw_lim_events 116 # nu
|
||||
system.cpu.rob.rob_reads 23467 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21056 # The number of ROB writes
|
||||
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4986 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10418 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5064 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 158 # number of misc regfile reads
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
|
||||
@@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
|
||||
@@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 432 # n
|
||||
system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 432 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
|
||||
@@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.218292
|
||||
system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -741,6 +741,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 17 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 17 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
|
||||
@@ -753,33 +755,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 331
|
||||
system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
|
||||
@@ -789,6 +791,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
@@ -809,16 +813,18 @@ system.cpu.l2cache.overall_misses::cpu.data 141 #
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -845,16 +851,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -877,16 +883,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -901,16 +907,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -919,7 +925,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
|
||||
@@ -927,23 +933,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 91
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
|
||||
@@ -967,7 +973,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 469 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30902500 # Number of ticks simulated
|
||||
final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000034 # Number of seconds simulated
|
||||
sim_ticks 33912500 # Number of ticks simulated
|
||||
final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 459853 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 459290 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2521006690 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291832 # Number of bytes of host memory used
|
||||
host_inst_rate 492168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 491565 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2961014581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292188 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu
|
||||
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
@@ -49,7 +49,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 61805 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 67825 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5624 # Number of instructions committed
|
||||
@@ -68,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu
|
||||
system.cpu.num_load_insts 1132 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 61805 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 67825 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 883 # Number of branches fetched
|
||||
@@ -108,17 +108,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5625 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
|
||||
@@ -138,14 +138,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n
|
||||
system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 137 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
|
||||
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067388
|
||||
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137
|
||||
system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
|
||||
@@ -202,27 +202,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
|
||||
@@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n
|
||||
system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 295 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
|
||||
@@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435
|
||||
system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -270,48 +270,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
@@ -330,18 +334,20 @@ system.cpu.l2cache.demand_misses::total 430 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 430 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -366,18 +372,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -398,18 +404,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -422,18 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -442,7 +448,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution
|
||||
@@ -450,27 +456,27 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 87
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 380 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
@@ -491,8 +497,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 430 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu
|
||||
sim_ticks 19923000 # Number of ticks simulated
|
||||
final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 93968 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93947 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 323084408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291680 # Number of bytes of host memory used
|
||||
host_inst_rate 101947 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101922 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 350504038 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292056 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27803500 # Number of ticks simulated
|
||||
final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30526500 # Number of ticks simulated
|
||||
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 506128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 505504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2635153066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292480 # Number of bytes of host memory used
|
||||
host_inst_rate 511867 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 511179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2925956101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292840 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
@@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu
|
||||
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 55607 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 61053 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
@@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu
|
||||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1121 # Number of branches fetched
|
||||
@@ -90,17 +90,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5370 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
|
||||
@@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n
|
||||
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 135 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
@@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262
|
||||
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
||||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
@@ -184,27 +184,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
|
||||
@@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n
|
||||
system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 257 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
|
||||
@@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850
|
||||
system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -258,39 +258,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257
|
||||
system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses
|
||||
@@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 389 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -451,9 +451,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
@@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 389 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000021 # Nu
|
||||
sim_ticks 20818000 # Number of ticks simulated
|
||||
final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 48919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189245943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313416 # Number of bytes of host memory used
|
||||
host_inst_rate 50154 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 90851 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 194020392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314048 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28359500 # Number of ticks simulated
|
||||
final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30886500 # Number of ticks simulated
|
||||
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 279983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 506758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1473373857 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311136 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 150745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 272977 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864611035 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310988 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu
|
||||
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 56719 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 61773 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
@@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu
|
||||
system.cpu.num_load_insts 1053 # Number of load instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1208 # Number of branches fetched
|
||||
@@ -93,17 +93,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 9748 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
|
||||
@@ -123,14 +123,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n
|
||||
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 134 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
||||
@@ -147,14 +147,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404
|
||||
system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134
|
||||
system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
|
||||
@@ -187,27 +187,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13956 # Number of data accesses
|
||||
@@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n
|
||||
system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses
|
||||
@@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217
|
||||
system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -261,39 +261,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228
|
||||
system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
|
||||
@@ -315,18 +315,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 361 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -351,18 +351,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -383,18 +383,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -452,7 +452,7 @@ system.cpu.toL2Bus.snoop_fanout::total 362 # Re
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 282 # Transaction distribution
|
||||
@@ -477,8 +477,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 361 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
||||
sim_ticks 24832500 # Number of ticks simulated
|
||||
final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155707227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297588 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 76523 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 149086837 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297164 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 12744 # Number of instructions simulated
|
||||
sim_ops 12744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -905,6 +905,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits
|
||||
@@ -955,6 +957,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
@@ -985,6 +989,8 @@ system.cpu.l2cache.demand_miss_latency::total 80021500
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -1085,7 +1091,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution
|
||||
@@ -1093,22 +1099,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 198
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
||||
sim_ticks 26944000 # Number of ticks simulated
|
||||
final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 95332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95323 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177899852 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294468 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 77815 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 77809 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 145216229 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294808 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000041 # Number of seconds simulated
|
||||
sim_ticks 41370500 # Number of ticks simulated
|
||||
final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000044 # Number of seconds simulated
|
||||
sim_ticks 44282500 # Number of ticks simulated
|
||||
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 454115 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292408 # Number of bytes of host memory used
|
||||
host_inst_rate 498046 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 497817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1453362434 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292760 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
@@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
||||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 82741 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 88565 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 15162 # Number of instructions committed
|
||||
@@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu
|
||||
system.cpu.num_load_insts 2231 # Number of load instructions
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 3363 # Number of branches fetched
|
||||
@@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 15207 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
||||
@@ -122,14 +122,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n
|
||||
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
@@ -148,14 +148,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633
|
||||
system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
||||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
@@ -188,27 +188,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
|
||||
@@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n
|
||||
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 280 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
|
||||
@@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411
|
||||
system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -262,39 +262,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280
|
||||
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
|
||||
@@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 416 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 416 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 416
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -453,7 +453,7 @@ system.cpu.toL2Bus.snoop_fanout::total 418 # Re
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 331 # Transaction distribution
|
||||
@@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 416 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.000062 # Nu
|
||||
sim_ticks 61610000 # Number of ticks simulated
|
||||
final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 402374 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 402048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3843418590 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 682268 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 589960 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 589258 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5631112330 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 681568 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6440 # Number of instructions simulated
|
||||
sim_ops 6440 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -546,17 +546,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 511 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 449 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 511 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 449 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu
|
||||
sim_ticks 49855000 # Number of ticks simulated
|
||||
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 351391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 406109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3506224066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 699088 # Number of bytes of host memory used
|
||||
host_inst_rate 371629 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 429475 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3707242713 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 698952 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4988 # Number of instructions simulated
|
||||
sim_ops 5770 # Number of ops (including micro ops) simulated
|
||||
@@ -640,17 +640,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 461 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 391 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 461 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 391 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks)
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu
|
||||
sim_ticks 58892000 # Number of ticks simulated
|
||||
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 489554 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 489001 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5114816745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679136 # Number of bytes of host memory used
|
||||
host_inst_rate 477419 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 476853 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4988311028 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679248 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
@@ -532,17 +532,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 528 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 434 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 528 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 434 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks)
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu
|
||||
sim_ticks 53334000 # Number of ticks simulated
|
||||
final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 497623 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 497044 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4772617450 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679800 # Number of bytes of host memory used
|
||||
host_inst_rate 408572 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 408151 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3919888285 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679628 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5548 # Number of instructions simulated
|
||||
sim_ops 5548 # Number of ops (including micro ops) simulated
|
||||
@@ -519,17 +519,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 397 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.007557 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.086709 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 468 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 397 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks)
|
||||
|
||||
@@ -4,10 +4,10 @@ sim_seconds 0.000056 # Nu
|
||||
sim_ticks 55844000 # Number of ticks simulated
|
||||
final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 284010 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 512497 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2773065846 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 698700 # Number of bytes of host memory used
|
||||
host_inst_rate 304186 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 548880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2969793661 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 698284 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5712 # Number of instructions simulated
|
||||
sim_ops 10314 # Number of ops (including micro ops) simulated
|
||||
@@ -518,17 +518,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 428 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 370 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 428 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 370 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks)
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.147041 # Number of seconds simulated
|
||||
sim_ticks 147041346500 # Number of ticks simulated
|
||||
final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.147149 # Number of seconds simulated
|
||||
sim_ticks 147148719500 # Number of ticks simulated
|
||||
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 870528 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 874854 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1413203999 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449664 # Number of bytes of host memory used
|
||||
host_seconds 104.05 # Real time elapsed on the host
|
||||
host_inst_rate 921343 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 925922 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1496788671 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449288 # Number of bytes of host memory used
|
||||
host_seconds 98.31 # Real time elapsed on the host
|
||||
sim_insts 90576862 # Number of instructions simulated
|
||||
sim_ops 91026991 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 36928 # Nu
|
||||
system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
@@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 294082693 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 294297439 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90576862 # Number of instructions committed
|
||||
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu
|
||||
system.cpu.num_load_insts 22475911 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 18732305 # Number of branches fetched
|
||||
@@ -208,18 +208,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91054081 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
|
||||
@@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n
|
||||
system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946799 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
@@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819
|
||||
system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795
|
||||
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
@@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
||||
@@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
|
||||
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
|
||||
@@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
|
||||
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -406,55 +406,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
|
||||
@@ -479,20 +483,22 @@ system.cpu.l2cache.demand_misses::total 15340 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 30304500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 30304500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11289500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11289500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 775310000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 805614500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30304500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 775310000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 805614500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -517,18 +523,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52520.797227 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52520.797227 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52509.302326 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52509.302326 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520.797227 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52517.242503 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520.797227 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52517.242503 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -549,18 +555,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15340
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 618540500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 618540500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24534500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24534500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9139500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9139500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24534500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 627680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 652214500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24534500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 627680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 652214500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -573,18 +579,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42517.218862 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42517.218862 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42520.797227 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42520.797227 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42509.302326 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42509.302326 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -593,8 +599,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
|
||||
@@ -602,22 +609,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
@@ -644,7 +651,7 @@ system.membus.snoop_fanout::max_value 0 # Re
|
||||
system.membus.snoop_fanout::total 15340 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 76964500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
|
||||
sim_ticks 87707000 # Number of ticks simulated
|
||||
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1726221 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 223510854 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306324 # Number of bytes of host memory used
|
||||
host_seconds 0.39 # Real time elapsed on the host
|
||||
host_inst_rate 1763094 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1763034 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 228285342 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306164 # Number of bytes of host memory used
|
||||
host_seconds 0.38 # Real time elapsed on the host
|
||||
sim_insts 677333 # Number of instructions simulated
|
||||
sim_ops 677333 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -232,6 +232,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 215 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.numCycles 173297 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
@@ -401,6 +403,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 278 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 278 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.numCycles 173296 # number of cpu cycles simulated
|
||||
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
@@ -571,6 +575,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.icache.writebacks::writebacks 278 # number of writebacks
|
||||
system.cpu2.icache.writebacks::total 278 # number of writebacks
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.numCycles 173297 # number of cpu cycles simulated
|
||||
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
@@ -740,6 +746,8 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.icache.writebacks::writebacks 279 # number of writebacks
|
||||
system.cpu3.icache.writebacks::total 279 # number of writebacks
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
|
||||
@@ -772,8 +780,10 @@ system.l2c.tags.age_task_id_blocks_1024::1 373 #
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 19424 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 19424 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
|
||||
@@ -842,8 +852,10 @@ system.l2c.overall_misses::cpu2.data 13 # nu
|
||||
system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
||||
system.l2c.overall_misses::total 559 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
|
||||
@@ -957,8 +969,9 @@ system.toL2Bus.snoop_filter.tot_snoops 0 # To
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
|
||||
@@ -974,15 +987,15 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,41 +1,41 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.133625 # Number of seconds simulated
|
||||
sim_ticks 133625300500 # Number of ticks simulated
|
||||
final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.134742 # Number of seconds simulated
|
||||
sim_ticks 134741611500 # Number of ticks simulated
|
||||
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1279205 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1279205 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1934942472 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304832 # Number of bytes of host memory used
|
||||
host_seconds 69.06 # Real time elapsed on the host
|
||||
host_inst_rate 1392855 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1392855 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2124451972 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305428 # Number of bytes of host memory used
|
||||
host_seconds 63.42 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 419712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10136000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10555712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 419712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 419712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7316416 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7316416 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6558 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 164933 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 114319 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 114319 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3140962 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 75853899 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 78994861 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3140962 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3140962 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 54753224 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 54753224 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 54753224 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3140962 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75853899 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 133748085 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 267250601 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 269483223 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88340673 # Number of instructions committed
|
||||
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu
|
||||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 267250601 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 269483223 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
@@ -129,18 +129,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 88438073 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.862376 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936464500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.862376 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
|
||||
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n
|
||||
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1944960000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1944960000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363504500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7363504500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9308464500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9308464500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9308464500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9308464500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32007.372544 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32007.372544 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.743638 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.743638 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45552.913225 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45552.913225 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168314 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168314 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168278 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
|
||||
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344
|
||||
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1884194000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1884194000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7219926500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7219926500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9104120500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9104120500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9104120500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9104120500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
@@ -226,27 +226,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31007.372544 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31007.372544 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50285.743638 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50285.743638 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.687345 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.687345 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913910 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913910 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
|
||||
@@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
|
||||
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 76436 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1269528000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1269528000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1269528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1269528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1269528000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1269528000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
|
||||
@@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864
|
||||
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16609.032393 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16609.032393 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16609.032393 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16609.032393 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -296,93 +296,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 74391 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 74391 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1193092000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1193092000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1193092000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1193092000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1193092000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1193092000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15609.032393 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15609.032393 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15609.032393 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15609.032393 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15609.032393 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15609.032393 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 131016 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30726.483059 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 246631 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.512406 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 131998 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27128.298594 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1976.305001 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1621.879464 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.827890 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060312 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.049496 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21188 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4750002 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4750002 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168314 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168314 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12698 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12698 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 69878 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 69878 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33271 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 33271 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 69878 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45969 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 115847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 69878 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45969 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 115847 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130880 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130880 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6558 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 6558 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27495 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 27495 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 6558 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158375 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 164933 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 6558 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158375 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 164933 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871230500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6871230500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 344676500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 344676500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1443699500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1443699500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 344676500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8314930000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8659606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 344676500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8314930000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8659606500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168314 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168314 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 33240 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 70696 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 116632 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 70696 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 116632 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5740 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 164148 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 341866000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 341866000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1637990000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1637990000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 341866000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9425532500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9767398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 341866000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9425532500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9767398500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -395,30 +401,30 @@ system.cpu.l2cache.demand_accesses::total 280780 # n
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911560 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911560 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085797 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085797 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452473 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452473 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085797 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775041 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.587410 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085797 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775041 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.587410 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.233038 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.233038 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52558.173224 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52558.173224 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52507.710493 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52507.710493 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52558.173224 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.531176 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52503.783354 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52558.173224 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.531176 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52503.783354 # average overall miss latency
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -427,70 +433,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 114319 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 114319 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1879 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1879 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130880 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6558 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6558 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27495 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27495 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6558 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158375 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 164933 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6558 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158375 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 164933 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5562430500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5562430500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 279096500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 279096500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1168749500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1168749500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 279096500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6731180000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7010276500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 279096500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6731180000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7010276500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 114382 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911560 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911560 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085797 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452473 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452473 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.587410 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.587410 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.233038 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.233038 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42558.173224 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42558.173224 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42507.710493 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42507.710493 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3862 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3862 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution
|
||||
@@ -498,51 +505,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23850112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 131016 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005626 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.074797 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 682573 99.44% 99.44% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3862 0.56% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 34053 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 114319 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 14713 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130880 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130880 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34053 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458898 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 458898 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17872128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17872128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadResp 33266 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 294098 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 292375 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 294098 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 294098 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 751484676 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 292375 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 824727676 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,41 +1,41 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.127296 # Number of seconds simulated
|
||||
sim_ticks 127296402500 # Number of ticks simulated
|
||||
final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.128077 # Number of seconds simulated
|
||||
sim_ticks 128076812500 # Number of ticks simulated
|
||||
final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 692014 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 883507 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1251758978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 324360 # Number of bytes of host memory used
|
||||
host_seconds 101.69 # Real time elapsed on the host
|
||||
host_inst_rate 787701 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1005673 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1433579724 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323992 # Number of bytes of host memory used
|
||||
host_seconds 89.34 # Real time elapsed on the host
|
||||
sim_insts 70373629 # Number of instructions simulated
|
||||
sim_ops 89847363 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
@@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 254592805 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 256153625 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70373629 # Number of instructions committed
|
||||
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu
|
||||
system.cpu.num_load_insts 22866262 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741486 # Number of branches fetched
|
||||
@@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 90690084 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83618 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 42492702 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42492702 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42576320 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42576320 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 30234 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 30234 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42569839 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 177392 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 183873 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
@@ -276,24 +276,24 @@ system.cpu.dcache.demand_accesses::cpu.data 42629968 #
|
||||
system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 128193 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128193 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1126 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1126 # number of overall MSHR hits
|
||||
system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128175 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
|
||||
@@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140
|
||||
system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
@@ -340,29 +340,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
|
||||
@@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
|
||||
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 18908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses
|
||||
@@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -412,93 +412,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 16890 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 16890 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 94651 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 95333 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30336.891349 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3016794 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3016794 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 128193 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 128193 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14958 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31426 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 31426 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14958 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 51136 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14958 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 51136 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3950 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3950 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21540 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21540 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3950 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 127770 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3950 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 127770 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605172 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258764 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027413 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 51431 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 127475 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -511,30 +517,30 @@ system.cpu.l2cache.demand_accesses::total 178906 # n
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.208906 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.208906 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406676 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406676 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.208906 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.714174 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.208906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -543,70 +549,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 86115 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 86115 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3950 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3950 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21540 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21540 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3950 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 127770 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3950 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 86150 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 15790 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 34314 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
|
||||
@@ -614,51 +621,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 94651 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2220672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 20663744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 95333 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 25490 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 86115 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 6526 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 25490 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348181 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 348181 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13688640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13688640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadResp 25194 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 6168 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 220592 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 219817 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 220592 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 220592 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 568748288 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 219817 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 641607492 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,44 +1,44 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.202233 # Number of seconds simulated
|
||||
sim_ticks 202232960500 # Number of ticks simulated
|
||||
final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.203116 # Number of seconds simulated
|
||||
sim_ticks 203115876500 # Number of ticks simulated
|
||||
final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1135828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1709104516 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304720 # Number of bytes of host memory used
|
||||
host_seconds 118.33 # Real time elapsed on the host
|
||||
host_inst_rate 1134042 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1148726 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1713866597 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305064 # Number of bytes of host memory used
|
||||
host_seconds 118.51 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7828288 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8353344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122317 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 130521 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2585007 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38540995 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 41126002 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2585007 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2585007 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 26867816 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26867816 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 26867816 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2585007 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38540995 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67993818 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 404465921 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 406231753 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 134398962 # Number of instructions committed
|
||||
@@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu
|
||||
system.cpu.num_load_insts 37275867 # Number of load instructions
|
||||
system.cpu.num_store_insts 20884381 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 406231752.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 12719095 # Number of branches fetched
|
||||
@@ -97,18 +97,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 136293798 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4087.268920 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268920 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
|
||||
@@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n
|
||||
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623254000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1623254000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6329554500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7952808500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7952808500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7952808500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7952808500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
||||
@@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35676.696191 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35676.696191 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.464341 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.464341 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52785.411813 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52785.411813 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -180,8 +180,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 123896 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 123865 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
|
||||
@@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663
|
||||
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577755000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577755000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802145500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7802145500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802145500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7802145500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
||||
@@ -212,29 +212,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34676.696191 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34676.696191 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.464341 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.464341 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 2004.181257 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.warmup_cycle 144582729500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181257 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id
|
||||
@@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n
|
||||
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 187024 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
|
||||
@@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390
|
||||
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -285,93 +285,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 184976 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 184976 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 98298 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 99021 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30843.659201 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 433831 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 130064 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.335519 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792048 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.109705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.039667 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.941420 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 30996 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 531 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17557 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 563 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945923 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 5588025 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 5588025 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 123896 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 123896 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3920 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3920 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178029 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 178029 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24461 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 24461 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 178029 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 28381 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 206410 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 178029 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 28381 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 206410 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 101259 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 101259 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8995 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 8995 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21038 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21038 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 8995 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 122297 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 131292 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 8995 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 122297 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 131292 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5316413000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5316413000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 472594500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 472594500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1104581000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1104581000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 472594500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6420994000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6893588500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 472594500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6420994000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6893588500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 123896 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 123896 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26289.730201 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863843 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.065157 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.802299 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.039797 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.941274 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 5588795 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 5588795 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 207181 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21053 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21053 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 122317 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 130521 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 122317 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 130521 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6025890500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252774500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252774500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7278665000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7767126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7278665000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7767126500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -384,30 +390,30 @@ system.cpu.l2cache.demand_accesses::total 337702 # n
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962730 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.962730 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.048095 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.048095 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462384 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462384 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.048095 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.811645 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.388781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.048095 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.811645 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.388781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52503.115772 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52503.115772 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52539.688716 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52539.688716 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.087841 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.087841 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52505.777199 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52505.777199 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462713 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462713 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.811777 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.386498 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.811777 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.386498 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.739809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.739809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747399 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747399 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59508.634626 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59508.634626 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -416,70 +422,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 85205 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 85205 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1630 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1630 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101259 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 101259 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8995 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8995 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21038 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21038 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8995 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 122297 # number of demand (read+write) MSHR misses
|
||||
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|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8995 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122297 # number of overall MSHR misses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303823000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303823000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 382644500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 382644500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 894201000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 894201000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 382644500 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 382644500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5198024000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5580668500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 85270 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21053 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21053 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 122317 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 130521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 130521 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042244500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042244500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055495000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6461916500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055495000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6461916500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962730 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962730 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.048095 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462384 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462384 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.388781 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.388781 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42503.115772 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42503.115772 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42539.688716 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42539.688716 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.087841 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.087841 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462713 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462713 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.386498 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.386498 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.739809 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.739809 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747399 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747399 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 184923 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 36455 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution
|
||||
@@ -487,51 +494,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17572736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 98298 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23804608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 41375360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 99021 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 433110 99.17% 99.17% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 436723 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 643471000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 30033 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 85205 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 11182 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101259 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101259 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 30033 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 358971 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 358971 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13855808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13855808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadResp 29257 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 10300 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101264 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101264 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 29257 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356612 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 356612 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13810624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 227790 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 226091 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 227790 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 226091 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 227790 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 569073488 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 226091 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 568572500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 656842488 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 652605000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,44 +1,44 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000053 # Number of seconds simulated
|
||||
sim_ticks 52651 # Number of ticks simulated
|
||||
final_tick 52651 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000054 # Number of seconds simulated
|
||||
sim_ticks 53711 # Number of ticks simulated
|
||||
final_tick 53711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 248880 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 445380 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_tick_rate 508906 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451636 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 53248 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 53248 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 47552 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 47552 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 832 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 832 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 743 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 743 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1011338816 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1011338816 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 903154736 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 903154736 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1914493552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1914493552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 833 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 743 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 833 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 743 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 44416 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54528 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 54528 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48448 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 48448 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 852 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 852 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 757 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 757 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1015211037 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1015211037 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 902012623 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 902012623 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917223660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1917223660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 852 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 757 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 852 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 757 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 8896 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 39488 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 53312 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 47552 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 54528 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 48448 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 97 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.mergedWrBursts 94 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 203 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 210 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::0 212 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
|
||||
@@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
|
||||
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 174 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 209 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 187 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 190 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 199 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
@@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 52632 # Total gap between requests
|
||||
system.mem_ctrls.totGap 53660 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 833 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 852 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 743 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 568 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 125 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.writePktSize::6 757 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 567 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 143 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
@@ -131,26 +131,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 26 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 34 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 35 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 35 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 35 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 35 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 37 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
@@ -180,70 +180,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 905.846154 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 828.873073 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 255.986324 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 1 1.10% 1.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 3 3.30% 4.40% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 4 4.40% 8.79% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 2 2.20% 10.99% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 5.49% 16.48% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.20% 18.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 5.49% 24.18% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 69 75.82% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 35 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 19.285714 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 19.012099 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.839205 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 10 28.57% 28.57% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 15 42.86% 71.43% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 6 17.14% 88.57% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::22-23 2 5.71% 94.29% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::24-25 1 2.86% 97.14% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::38-39 1 2.86% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 35 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 35 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.628571 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 17.590452 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.165325 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 10 28.57% 28.57% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 2 5.71% 34.29% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 14 40.00% 74.29% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 9 25.71% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 35 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 5779 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 18965 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3470 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 889.191489 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 796.949082 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 278.173972 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 2 2.13% 2.13% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 4 4.26% 6.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 5 5.32% 11.70% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 3 3.19% 14.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 1 1.06% 15.96% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 2 2.13% 18.09% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 20.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 5.32% 25.53% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 70 74.47% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 36 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 19.277778 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 18.954063 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 4.046947 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 3 8.33% 8.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 9 25.00% 33.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 11 30.56% 63.89% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 5 13.89% 77.78% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::22-23 6 16.67% 94.44% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::24-25 1 2.78% 97.22% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::38-39 1 2.78% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 36 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 36 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.555556 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 17.508645 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.297127 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 13 36.11% 36.11% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 2.78% 38.89% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 12 33.33% 72.22% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 9 25.00% 97.22% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::20 1 2.78% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 36 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 5835 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 19382 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 8.18 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 843.59 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 750.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1012.55 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 903.15 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 27.18 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 849.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 753.07 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1015.21 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 902.01 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 12.45 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 6.59 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 5.86 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.32 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.38 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 607 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 610 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 87.46 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 94.43 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 33.40 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 90.82 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 627480 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 348600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 7637760 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 5681664 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.busUtil 12.52 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 6.64 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 5.88 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.35 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.46 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 622 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 94.27 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 33.35 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 90.62 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 7700160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 5816448 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 49463916 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 1052.961427 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.totalEnergy 49696380 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 1057.909997 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
@@ -266,360 +269,354 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 #
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 965
|
||||
system.ruby.outstanding_req_hist::mean 15.764767
|
||||
system.ruby.outstanding_req_hist::gmean 15.657041
|
||||
system.ruby.outstanding_req_hist::stdev 1.204074
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.41% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.43% 11.09% | 858 88.91% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 965
|
||||
system.ruby.outstanding_req_hist::samples 972
|
||||
system.ruby.outstanding_req_hist::mean 15.762346
|
||||
system.ruby.outstanding_req_hist::gmean 15.655254
|
||||
system.ruby.outstanding_req_hist::stdev 1.201656
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.65% | 94 9.67% 11.32% | 862 88.68% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 972
|
||||
system.ruby.latency_hist::bucket_size 256
|
||||
system.ruby.latency_hist::max_bucket 2559
|
||||
system.ruby.latency_hist::samples 950
|
||||
system.ruby.latency_hist::mean 871.068421
|
||||
system.ruby.latency_hist::gmean 461.645451
|
||||
system.ruby.latency_hist::stdev 364.947641
|
||||
system.ruby.latency_hist | 141 14.84% 14.84% | 6 0.63% 15.47% | 4 0.42% 15.89% | 461 48.53% 64.42% | 326 34.32% 98.74% | 12 1.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 950
|
||||
system.ruby.latency_hist::samples 957
|
||||
system.ruby.latency_hist::mean 881.794148
|
||||
system.ruby.latency_hist::gmean 495.949804
|
||||
system.ruby.latency_hist::stdev 359.464211
|
||||
system.ruby.latency_hist | 135 14.11% 14.11% | 6 0.63% 14.73% | 4 0.42% 15.15% | 442 46.19% 61.34% | 349 36.47% 97.81% | 21 2.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 957
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 86
|
||||
system.ruby.hit_latency_hist::samples 75
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 86 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 86
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 75
|
||||
system.ruby.miss_latency_hist::bucket_size 256
|
||||
system.ruby.miss_latency_hist::max_bucket 2559
|
||||
system.ruby.miss_latency_hist::samples 864
|
||||
system.ruby.miss_latency_hist::mean 957.672454
|
||||
system.ruby.miss_latency_hist::gmean 850.170322
|
||||
system.ruby.miss_latency_hist::stdev 252.014806
|
||||
system.ruby.miss_latency_hist | 55 6.37% 6.37% | 6 0.69% 7.06% | 4 0.46% 7.52% | 461 53.36% 60.88% | 326 37.73% 98.61% | 12 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 864
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 84 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 819 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 903 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 46 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 5 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 32 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 833 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 865 # Number of cache demand accesses
|
||||
system.ruby.miss_latency_hist::samples 882
|
||||
system.ruby.miss_latency_hist::mean 956.691610
|
||||
system.ruby.miss_latency_hist::gmean 840.701090
|
||||
system.ruby.miss_latency_hist::stdev 261.829138
|
||||
system.ruby.miss_latency_hist | 60 6.80% 6.80% | 6 0.68% 7.48% | 4 0.45% 7.94% | 442 50.11% 58.05% | 349 39.57% 97.62% | 21 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 882
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 75 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 832 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 907 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 76 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 852 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 882 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 9.000779
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 859
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1720
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 864
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 61848
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13760
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 6912
|
||||
system.ruby.network.routers1.percent_links_utilized 17.230442
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 1664
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1603
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1720
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 1488
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1694
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 119808
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 115416
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13760
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 11904
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13552
|
||||
system.ruby.network.routers2.percent_links_utilized 8.227289
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 743
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 1488
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 831
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 53496
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 11904
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6648
|
||||
system.ruby.network.routers3.percent_links_utilized 11.486012
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 1664
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1603
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1720
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 1488
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1695
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 119808
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 115416
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13760
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 11904
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13560
|
||||
system.ruby.network.msg_count.Request_Control 5094
|
||||
system.ruby.network.msg_count.Response_Data 4992
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 96
|
||||
system.ruby.network.msg_count.Writeback_Data 4808
|
||||
system.ruby.network.msg_count.Writeback_Control 9624
|
||||
system.ruby.network.msg_count.Unblock_Control 5084
|
||||
system.ruby.network.msg_byte.Request_Control 40752
|
||||
system.ruby.network.msg_byte.Response_Data 359424
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 6912
|
||||
system.ruby.network.msg_byte.Writeback_Data 346176
|
||||
system.ruby.network.msg_byte.Writeback_Control 76992
|
||||
system.ruby.network.msg_byte.Unblock_Control 40672
|
||||
system.ruby.network.routers0.throttle0.link_utilization 8.201174
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers0.throttle1.link_utilization 9.800384
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 859
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 864
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 61848
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 6912
|
||||
system.ruby.network.routers1.throttle0.link_utilization 17.616949
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 859
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 863
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 61848
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 6904
|
||||
system.ruby.network.routers1.throttle1.link_utilization 16.843935
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 744
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 831
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 53568
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6648
|
||||
system.ruby.network.routers2.throttle0.link_utilization 8.637063
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 743
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 831
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 53496
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6648
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.817515
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers3.throttle0.link_utilization 8.201174
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 32
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2304
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers3.throttle1.link_utilization 17.617899
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 865
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 832
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 859
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 860
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 864
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 6920
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 59904
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 61848
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 6880
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 6912
|
||||
system.ruby.network.routers3.throttle2.link_utilization 8.638962
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 833
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 744
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 744
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 831
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6664
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 53568
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 5952
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6648
|
||||
system.ruby.network.routers0.percent_links_utilized 9.006070
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 877
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1754
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 882
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 63144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14032
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7056
|
||||
system.ruby.network.routers1.percent_links_utilized 17.246933
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 1704
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1635
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1754
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 1516
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1732
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 122688
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 117720
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14032
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12128
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13856
|
||||
system.ruby.network.routers2.percent_links_utilized 8.238536
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 757
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 1516
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 851
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54504
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12128
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6808
|
||||
system.ruby.network.routers3.percent_links_utilized 11.497024
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 1704
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1635
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1754
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 1516
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1733
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 122688
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 117720
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14032
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12128
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13864
|
||||
system.ruby.network.msg_count.Request_Control 5202
|
||||
system.ruby.network.msg_count.Response_Data 5112
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 90
|
||||
system.ruby.network.msg_count.Writeback_Data 4904
|
||||
system.ruby.network.msg_count.Writeback_Control 9810
|
||||
system.ruby.network.msg_count.Unblock_Control 5198
|
||||
system.ruby.network.msg_byte.Request_Control 41616
|
||||
system.ruby.network.msg_byte.Response_Data 368064
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 6480
|
||||
system.ruby.network.msg_byte.Writeback_Data 353088
|
||||
system.ruby.network.msg_byte.Writeback_Control 78480
|
||||
system.ruby.network.msg_byte.Unblock_Control 41584
|
||||
system.ruby.network.routers0.throttle0.link_utilization 8.205954
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers0.throttle1.link_utilization 9.806185
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 877
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 882
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 63144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7056
|
||||
system.ruby.network.routers1.throttle0.link_utilization 17.649085
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 877
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 881
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 63144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7048
|
||||
system.ruby.network.routers1.throttle1.link_utilization 16.844780
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 758
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 851
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 54576
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6808
|
||||
system.ruby.network.routers2.throttle0.link_utilization 8.633241
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 757
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 851
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 54504
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6808
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.843831
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers3.throttle0.link_utilization 8.205954
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 30
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2160
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers3.throttle1.link_utilization 17.650016
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 882
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 852
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 877
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 877
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 882
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7056
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61344
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 63144
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7016
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7056
|
||||
system.ruby.network.routers3.throttle2.link_utilization 8.635103
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 852
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 758
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 758
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 851
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6816
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 54576
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6064
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6808
|
||||
system.ruby.LD.latency_hist::bucket_size 256
|
||||
system.ruby.LD.latency_hist::max_bucket 2559
|
||||
system.ruby.LD.latency_hist::samples 52
|
||||
system.ruby.LD.latency_hist::mean 921.692308
|
||||
system.ruby.LD.latency_hist::gmean 521.813634
|
||||
system.ruby.LD.latency_hist::stdev 317.419654
|
||||
system.ruby.LD.latency_hist | 5 9.62% 9.62% | 0 0.00% 9.62% | 0 0.00% 9.62% | 32 61.54% 71.15% | 14 26.92% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 52
|
||||
system.ruby.LD.latency_hist::samples 50
|
||||
system.ruby.LD.latency_hist::mean 914.500000
|
||||
system.ruby.LD.latency_hist::gmean 544.079764
|
||||
system.ruby.LD.latency_hist::stdev 318.769653
|
||||
system.ruby.LD.latency_hist | 5 10.00% 10.00% | 0 0.00% 10.00% | 0 0.00% 10.00% | 30 60.00% 70.00% | 13 26.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 50
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 5
|
||||
system.ruby.LD.hit_latency_hist::samples 4
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 5
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 4
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 256
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 2559
|
||||
system.ruby.LD.miss_latency_hist::samples 47
|
||||
system.ruby.LD.miss_latency_hist::mean 1019.638298
|
||||
system.ruby.LD.miss_latency_hist::gmean 1015.343067
|
||||
system.ruby.LD.miss_latency_hist::stdev 98.825148
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 32 68.09% 68.09% | 14 29.79% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 47
|
||||
system.ruby.LD.miss_latency_hist::samples 46
|
||||
system.ruby.LD.miss_latency_hist::mean 993.934783
|
||||
system.ruby.LD.miss_latency_hist::gmean 940.906082
|
||||
system.ruby.LD.miss_latency_hist::stdev 173.263243
|
||||
system.ruby.LD.miss_latency_hist | 1 2.17% 2.17% | 0 0.00% 2.17% | 0 0.00% 2.17% | 30 65.22% 67.39% | 13 28.26% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 46
|
||||
system.ruby.ST.latency_hist::bucket_size 256
|
||||
system.ruby.ST.latency_hist::max_bucket 2559
|
||||
system.ruby.ST.latency_hist::samples 850
|
||||
system.ruby.ST.latency_hist::mean 913.334118
|
||||
system.ruby.ST.latency_hist::gmean 517.508162
|
||||
system.ruby.ST.latency_hist::stdev 322.997582
|
||||
system.ruby.ST.latency_hist | 88 10.35% 10.35% | 6 0.71% 11.06% | 4 0.47% 11.53% | 429 50.47% 62.00% | 312 36.71% 98.71% | 11 1.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 850
|
||||
system.ruby.ST.latency_hist::samples 857
|
||||
system.ruby.ST.latency_hist::mean 927.439907
|
||||
system.ruby.ST.latency_hist::gmean 556.916459
|
||||
system.ruby.ST.latency_hist::stdev 312.242258
|
||||
system.ruby.ST.latency_hist | 80 9.33% 9.33% | 6 0.70% 10.04% | 4 0.47% 10.50% | 412 48.07% 58.58% | 336 39.21% 97.78% | 19 2.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 857
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 79
|
||||
system.ruby.ST.hit_latency_hist::samples 71
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 79 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 79
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 71 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 71
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 256
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 2559
|
||||
system.ruby.ST.miss_latency_hist::samples 771
|
||||
system.ruby.ST.miss_latency_hist::mean 1006.815824
|
||||
system.ruby.ST.miss_latency_hist::gmean 981.740975
|
||||
system.ruby.ST.miss_latency_hist::stdev 144.511842
|
||||
system.ruby.ST.miss_latency_hist | 9 1.17% 1.17% | 6 0.78% 1.95% | 4 0.52% 2.46% | 429 55.64% 58.11% | 312 40.47% 98.57% | 11 1.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 771
|
||||
system.ruby.ST.miss_latency_hist::samples 786
|
||||
system.ruby.ST.miss_latency_hist::mean 1011.125954
|
||||
system.ruby.ST.miss_latency_hist::gmean 985.869507
|
||||
system.ruby.ST.miss_latency_hist::stdev 147.214582
|
||||
system.ruby.ST.miss_latency_hist | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 412 52.42% 54.83% | 336 42.75% 97.58% | 19 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 786
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 48
|
||||
system.ruby.IFETCH.latency_hist::mean 67.770833
|
||||
system.ruby.IFETCH.latency_hist::gmean 53.478769
|
||||
system.ruby.IFETCH.latency_hist::stdev 34.601217
|
||||
system.ruby.IFETCH.latency_hist | 5 10.42% 10.42% | 12 25.00% 35.42% | 27 56.25% 91.67% | 0 0.00% 91.67% | 3 6.25% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 48
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2
|
||||
system.ruby.IFETCH.latency_hist::samples 50
|
||||
system.ruby.IFETCH.latency_hist::mean 66.720000
|
||||
system.ruby.IFETCH.latency_hist::gmean 61.968921
|
||||
system.ruby.IFETCH.latency_hist::stdev 27.740812
|
||||
system.ruby.IFETCH.latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 50
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 46
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 70.673913
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 63.579883
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 32.306212
|
||||
system.ruby.IFETCH.miss_latency_hist | 3 6.52% 6.52% | 12 26.09% 32.61% | 27 58.70% 91.30% | 0 0.00% 91.30% | 3 6.52% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 46
|
||||
system.ruby.Directory_Controller.GETX 749 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 84 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 744 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 748 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 743 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 832 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 743 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 687 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 79 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 743 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETX 62 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 744 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 79 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 748 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 748 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 743 0.00% 0.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 50
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 66.720000
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 61.968921
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 27.740812
|
||||
system.ruby.IFETCH.miss_latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 50
|
||||
system.ruby.Directory_Controller.GETX 763 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 89 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 758 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 84 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 4 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 763 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 757 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 852 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 757 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 700 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 85 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 757 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETX 63 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 4 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 758 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 84 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 85 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 4 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 4 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 763 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 763 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 757 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Load 52 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 60 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 859 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 77732 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 84 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 780 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 860 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 771 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 780 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 47 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 772 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 5 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 67 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 771 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 12 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30528 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 771 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 43624 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 771 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.L1_Replacement 28 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 771 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 2687 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 84 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Ifetch 12 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 79286 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 89 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 793 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 877 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 792 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 786 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 87 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 7 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 3 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 784 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31474 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 785 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 44509 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.L1_Replacement 57 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 2365 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 89 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 7 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 87 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Ifetch 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 779 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 93 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 772 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 779 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 748 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 832 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 778 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 744 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 83 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 780 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 824 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 84 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 749 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 779 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 790 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 96 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 786 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 790 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTS_only 87 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 763 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 852 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 87 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 790 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 758 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 88 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 793 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 844 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 89 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 763 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 87 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 790 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 86 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 23 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 744 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 778 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 84 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 83 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 748 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 748 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 748 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 758 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 87 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 790 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 89 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 88 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 763 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 763 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 763 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 23 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 744 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 7 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 758 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
||||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 8340026204 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263964 # Number of bytes of host memory used
|
||||
host_seconds 11.99 # Real time elapsed on the host
|
||||
host_tick_rate 8352384426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264628 # Number of bytes of host memory used
|
||||
host_seconds 11.97 # Real time elapsed on the host
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory
|
||||
@@ -285,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664
|
||||
system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 11.7 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 11025639931 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.occupancy 11025969759 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 11.0 # Layer utilization (%)
|
||||
system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
@@ -392,21 +392,21 @@ system.monitor.writeBandwidthHist::total 100 # Hi
|
||||
system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s)
|
||||
system.monitor.totalWrittenBytes 106680256 # Number of bytes written
|
||||
system.monitor.readLatencyHist::samples 1666397 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 80828.076592 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 75646.741335 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 40157.798719 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 80828.757102 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 75647.211665 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 40158.670662 # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 453129 27.19% 27.19% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 1001108 60.08% 87.27% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 453126 27.19% 27.19% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 1001111 60.08% 87.27% # Read request-response latency
|
||||
system.monitor.readLatencyHist::98304-131071 83302 5.00% 92.27% # Read request-response latency
|
||||
system.monitor.readLatencyHist::131072-163839 62543 3.75% 96.02% # Read request-response latency
|
||||
system.monitor.readLatencyHist::163840-196607 26583 1.60% 97.62% # Read request-response latency
|
||||
system.monitor.readLatencyHist::196608-229375 8788 0.53% 98.14% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 7679 0.46% 98.61% # Read request-response latency
|
||||
system.monitor.readLatencyHist::229376-262143 7677 0.46% 98.61% # Read request-response latency
|
||||
system.monitor.readLatencyHist::262144-294911 7849 0.47% 99.08% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 7873 0.47% 99.55% # Read request-response latency
|
||||
system.monitor.readLatencyHist::294912-327679 7874 0.47% 99.55% # Read request-response latency
|
||||
system.monitor.readLatencyHist::327680-360447 4044 0.24% 99.79% # Read request-response latency
|
||||
system.monitor.readLatencyHist::360448-393215 1554 0.09% 99.88% # Read request-response latency
|
||||
system.monitor.readLatencyHist::360448-393215 1555 0.09% 99.88% # Read request-response latency
|
||||
system.monitor.readLatencyHist::393216-425983 891 0.05% 99.94% # Read request-response latency
|
||||
system.monitor.readLatencyHist::425984-458751 671 0.04% 99.98% # Read request-response latency
|
||||
system.monitor.readLatencyHist::458752-491519 316 0.02% 100.00% # Read request-response latency
|
||||
@@ -417,9 +417,9 @@ system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00%
|
||||
system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::total 1666397 # Read request-response latency
|
||||
system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::mean 19578.682028 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::gmean 19571.486505 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::stdev 552.701557 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::mean 19652.383883 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::gmean 19632.845881 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::stdev 964.266043 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency
|
||||
@@ -429,13 +429,13 @@ system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00%
|
||||
system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::16384-18431 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::18432-20479 1622054 97.31% 97.31% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::20480-22527 29447 1.77% 99.08% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::22528-24575 12825 0.77% 99.85% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::24576-26623 2552 0.15% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::18432-20479 1607382 96.43% 96.43% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::20480-22527 29447 1.77% 98.20% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::22528-24575 12825 0.77% 98.97% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::24576-26623 7107 0.43% 99.39% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::26624-28671 4858 0.29% 99.68% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::28672-30719 4531 0.27% 99.96% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::30720-32767 728 0.04% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency
|
||||
|
||||
@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
||||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 16305869412 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265756 # Number of bytes of host memory used
|
||||
host_seconds 6.13 # Real time elapsed on the host
|
||||
host_tick_rate 16291006908 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266948 # Number of bytes of host memory used
|
||||
host_seconds 6.14 # Real time elapsed on the host
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
|
||||
@@ -143,8 +143,8 @@ system.monitor.writeBandwidthHist::total 100 # Hi
|
||||
system.monitor.averageWriteBandwidth 8533120 0.00% 0.00% # Average write bandwidth (bytes/s)
|
||||
system.monitor.totalWrittenBytes 853312 # Number of bytes written
|
||||
system.monitor.readLatencyHist::samples 1 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 32000 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 32000.000000 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 35000 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 35000.000000 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev nan # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-2047 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::2048-4095 0 0.00% 0.00% # Read request-response latency
|
||||
@@ -161,15 +161,15 @@ system.monitor.readLatencyHist::22528-24575 0 0.00% 0.00% #
|
||||
system.monitor.readLatencyHist::24576-26623 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::26624-28671 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::28672-30719 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::30720-32767 1 100.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-34815 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::34816-36863 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::30720-32767 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-34815 0 0.00% 0.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::34816-36863 1 100.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency
|
||||
system.monitor.readLatencyHist::total 1 # Read request-response latency
|
||||
system.monitor.writeLatencyHist::samples 13333 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::mean 32000.024601 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::gmean 32000.024475 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::mean 39000.024601 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::gmean 39000.024498 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::stdev 2.840599 # Write request-response latency
|
||||
system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
|
||||
@@ -186,11 +186,11 @@ system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00%
|
||||
system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::28672-30719 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::30720-32767 13333 100.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::30720-32767 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::32768-34815 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::34816-36863 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::36864-38911 0 0.00% 0.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::38912-40959 13333 100.00% 100.00% # Write request-response latency
|
||||
system.monitor.writeLatencyHist::total 13333 # Write request-response latency
|
||||
system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time
|
||||
system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.118729 # Number of seconds simulated
|
||||
sim_ticks 118729316500 # Number of ticks simulated
|
||||
final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.118763 # Number of seconds simulated
|
||||
sim_ticks 118762761500 # Number of ticks simulated
|
||||
final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1432938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1432938 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1851208744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301400 # Number of bytes of host memory used
|
||||
host_seconds 64.14 # Real time elapsed on the host
|
||||
host_inst_rate 1561278 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1561278 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2017578166 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301004 # Number of bytes of host memory used
|
||||
host_seconds 58.86 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu
|
||||
system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 237458633 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 237525523 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903056 # Number of instructions committed
|
||||
@@ -82,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu
|
||||
system.cpu.num_load_insts 19996208 # Number of load instructions
|
||||
system.cpu.num_store_insts 6501126 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 237458633 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 237525523 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
@@ -122,19 +122,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91903089 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043368 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043368 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
|
||||
@@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n
|
||||
system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2223 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
@@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
||||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23424000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23424000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 93300000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 93300000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116724000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 116724000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116724000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 116724000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
@@ -221,24 +221,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052751 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052751 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
||||
@@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n
|
||||
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8510 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
|
||||
@@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 6681 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 6681 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 212202500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 212202500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 212202500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 212202500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 212202500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 212202500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24935.663925 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24935.663925 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070486 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017940 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257369 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits
|
||||
@@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 4765 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137603000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137603000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22155000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22155000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.190767 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4765
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73185000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73185000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 111393000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 111393000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111393000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 202513000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111393000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 202513000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.190767 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.190767 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution
|
||||
@@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 475
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 17571 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
@@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4765 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.230174 # Number of seconds simulated
|
||||
sim_ticks 230173520500 # Number of ticks simulated
|
||||
final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.230198 # Number of seconds simulated
|
||||
sim_ticks 230197694500 # Number of ticks simulated
|
||||
final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1035845 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1387457275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319880 # Number of bytes of host memory used
|
||||
host_seconds 165.90 # Real time elapsed on the host
|
||||
host_inst_rate 1005681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1060242 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1347195966 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319496 # Number of bytes of host memory used
|
||||
host_seconds 170.87 # Real time elapsed on the host
|
||||
sim_insts 171842484 # Number of instructions simulated
|
||||
sim_ops 181165371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu
|
||||
system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
@@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 460347041 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 460395389 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 171842484 # Number of instructions committed
|
||||
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu
|
||||
system.cpu.num_load_insts 27896144 # Number of load instructions
|
||||
system.cpu.num_store_insts 12644635 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300312 # Number of branches fetched
|
||||
@@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 181650743 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
||||
@@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n
|
||||
system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
@@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788
|
||||
system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
@@ -329,26 +329,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
||||
@@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n
|
||||
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3051 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
|
||||
@@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
||||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -402,44 +402,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1506 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1506 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
||||
@@ -449,8 +451,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits
|
||||
@@ -475,20 +479,22 @@ system.cpu.l2cache.demand_misses::total 3453 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90862500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 90862500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33203000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33203000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -513,18 +519,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -545,18 +551,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3453
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73572500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73572500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 26883000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 26883000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73572500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73323500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 146896000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73572500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73323500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 146896000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -569,18 +575,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -589,8 +595,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
|
||||
@@ -598,22 +605,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 689
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
@@ -638,9 +645,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3453 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.270563 # Number of seconds simulated
|
||||
sim_ticks 270563083500 # Number of ticks simulated
|
||||
final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.270600 # Number of seconds simulated
|
||||
sim_ticks 270599529500 # Number of ticks simulated
|
||||
final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1207450 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1688810940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300136 # Number of bytes of host memory used
|
||||
host_seconds 160.21 # Real time elapsed on the host
|
||||
host_inst_rate 1167307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1167308 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1632884817 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300512 # Number of bytes of host memory used
|
||||
host_seconds 165.72 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 230208 # Nu
|
||||
system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 541126167 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 541199059 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 193444518 # Number of instructions committed
|
||||
@@ -50,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu
|
||||
system.cpu.num_load_insts 57735091 # Number of load instructions
|
||||
system.cpu.num_store_insts 18998867 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 15132745 # Number of branches fetched
|
||||
@@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 193445773 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
||||
@@ -127,16 +127,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n
|
||||
system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1575 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
|
||||
@@ -157,16 +157,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -187,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575
|
||||
system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26892000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26892000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 58158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 54000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 54000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 85050000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 85050000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 85050000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 85050000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
|
||||
@@ -207,26 +207,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
||||
@@ -248,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n
|
||||
system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12288 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
|
||||
@@ -266,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064
|
||||
system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -280,44 +280,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 10362 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10362 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
|
||||
@@ -327,8 +329,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
|
||||
@@ -347,20 +351,22 @@ system.cpu.l2cache.demand_misses::total 5173 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 188843000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 188843000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26145000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 26145000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -385,18 +391,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -417,18 +423,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5173
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45815000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45815000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 152873000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 152873000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21165000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21165000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 152873000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66980000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 219853000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 152873000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66980000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 219853000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -441,18 +447,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -461,8 +467,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution
|
||||
@@ -470,22 +476,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 498
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
@@ -510,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5173 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.250954 # Number of seconds simulated
|
||||
sim_ticks 250953958500 # Number of ticks simulated
|
||||
final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.250987 # Number of seconds simulated
|
||||
sim_ticks 250987138500 # Number of ticks simulated
|
||||
final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 759533 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1443220819 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 343748 # Number of bytes of host memory used
|
||||
host_seconds 173.88 # Real time elapsed on the host
|
||||
host_inst_rate 735776 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1233228 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1398263201 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 343356 # Number of bytes of host memory used
|
||||
host_seconds 179.50 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 181760 # Nu
|
||||
system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501907917 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 501974277 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 132071193 # Number of instructions committed
|
||||
@@ -53,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu
|
||||
system.cpu.num_load_insts 56649587 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515717 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 12326938 # Number of branches fetched
|
||||
@@ -93,19 +93,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 221363385 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
|
||||
@@ -126,14 +126,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n
|
||||
system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1905 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
||||
@@ -150,14 +150,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905
|
||||
system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17365500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17365500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102451500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 102451500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102451500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 102451500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
|
||||
@@ -192,29 +192,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
|
||||
@@ -231,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n
|
||||
system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4694 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
|
||||
@@ -249,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027
|
||||
system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -263,55 +263,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2836 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2836 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits
|
||||
@@ -336,20 +340,22 @@ system.cpu.l2cache.demand_misses::total 4735 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 149117500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 149117500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16801500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 16801500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses)
|
||||
@@ -374,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -406,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4735
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66937500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66937500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 120717500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 120717500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13601500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13601500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120717500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 80539000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 201256500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120717500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 80539000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 201256500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses
|
||||
@@ -430,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
@@ -450,8 +456,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
|
||||
@@ -459,22 +466,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 327
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
@@ -501,9 +508,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4735 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
Reference in New Issue
Block a user