diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 228149115c..e55894cc8a 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1194,7 +1194,7 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
 
     SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
     SoftwareStep *ss = sd->getSstep();
-    new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest, new_cpsr.width);
+    new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest);
 
     return new_cpsr;
 }
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index ef6ad63225..21ad84c371 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -643,7 +643,7 @@ WatchPoint::compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas,
 
 bool
 SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
-                                     ExceptionLevel dest, bool aarch32)
+                                     ExceptionLevel dest)
 {
     bool SS_bit = false;
     bool enabled_src = false;
@@ -652,9 +652,7 @@ SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
 
         bool enabled_dst = false;
         bool secure = isSecureBelowEL3(tc) || dest == EL3;
-//        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-//        if (cpsr.width) {
-        if (ELIs32(tc, dest)) {
+        if (spsr.width) {
             enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
                                                       spsr.d == 1);
         } else {
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 953a2dcda7..7a96d42033 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -210,7 +210,7 @@ class SoftwareStep
     {}
 
     bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
-                                ExceptionLevel dest, bool aarch32);
+                                ExceptionLevel dest);
     bool advanceSS(ThreadContext *tc);
 
     inline void