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arch-gcn3,gpu-compute: Move GCN3 specific TLB to arch

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Move GpuTLB and TLBCoalescer to GCN3 as the TLB format is specific to
GCN3 and SE mode / APU simulation. Vega will have its own TLB,
coalescer, and walker suitable for a dGPU. This also adds a using alias
for the TLB translation state to reduce the number of references to
TheISA and X86ISA. X86 specific includes are also removed.

Change-Id: I34448bb4e5ddb9980b34a55bc717bbcea0e03db5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2021-09-01 14:30:35 -05:00
parent b459e2caed
commit 3112a7f0d0
12 changed files with 57 additions and 55 deletions
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3
src/gpu-compute/SConscript
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@@ -39,7 +39,6 @@ if not env['BUILD_GPU']:
SimObject('GPU.py')
SimObject('GPUStaticInstFlags.py')
SimObject('LdsState.py')
SimObject('X86GPUTLB.py')
Source('comm.cc')
Source('compute_unit.cc')
@@ -54,7 +53,6 @@ Source('gpu_dyn_inst.cc')
Source('gpu_exec_context.cc')
Source('gpu_render_driver.cc')
Source('gpu_static_inst.cc')
Source('gpu_tlb.cc')
Source('lds_state.cc')
Source('local_memory_pipeline.cc')
Source('pool_manager.cc')
@@ -69,7 +67,6 @@ Source('shader.cc')
Source('dyn_pool_manager.cc')
Source('simple_pool_manager.cc')
Source('static_register_manager_policy.cc')
Source('tlb_coalescer.cc')
Source('vector_register_file.cc')
Source('wavefront.cc')