X86: Fix the microcode for sign/zero extending moves that use high byte registers.

2008-09-03 00:52:54 -04:00
parent 4aa017affc
commit 30bc897613
25 changed files with 116 additions and 108 deletions
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -126,7 +126,8 @@ def macroop MOVSXD_R_P {
 };

 def macroop MOVSX_B_R_R {
-    sexti reg, regm, 7
+    mov t1, t1, regm, dataSize=1
+    sexti reg, t1, 7
 };

 def macroop MOVSX_B_R_M {
@@ -160,7 +161,8 @@ def macroop MOVSX_W_R_P {
 #

 def macroop MOVZX_B_R_R {
-    zexti reg, regm, 7
+    mov t1, t1, regm, dataSize=1
+    zexti reg, t1, 7
 };

 def macroop MOVZX_B_R_M {