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arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling

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The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only.  This patch eliminates the per-CPU
storage of these values that are simply computed.

Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
This commit is contained in:
Curtis Dunham
2017-01-31 17:11:24 +00:00
committed by Andreas Sandberg
parent bbdd34d628
commit 2f14baaabc
3 changed files with 38 additions and 51 deletions
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2
util/cpt_upgraders/arm-gicv2-banked-regs.py
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@@ -52,7 +52,6 @@ def upgrader(cpt):
b_intEnabled = intEnabled[0]
b_pendingInt = pendingInt[0]
b_activeInt = activeInt[0]
b_cpuTarget = cpuTarget[0:32]
del intEnabled[0]
del pendingInt[0]
@@ -78,4 +77,3 @@ def upgrader(cpt):
cpt.set(new_sec, 'pendingInt', b_pendingInt)
cpt.set(new_sec, 'activeInt', b_activeInt)
cpt.set(new_sec, 'intPriority',' '.join(intPriority))
cpt.set(new_sec, 'cpuTarget', ' '.join(b_cpuTarget))