diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0f54906ac1..c36848ecf6 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -198,100 +198,100 @@ static_assert(sizeof(ArmFault::aarch64FaultSources) ==
 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
 //         {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
 //         {A, F} disable, class, stat
-template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = {
+template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals(
     // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
     // location in AArch64)
     "Reset",                 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
-    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = {
+    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals(
     "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
-    4, 2, 0, 0, true,  false, false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = {
+    4, 2, 0, 0, true,  false, false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals(
     "Supervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = {
+    4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals(
     "Secure Monitor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
-    4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = {
+    4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals(
     "Hypervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
-    4, 4, 4, 4, true,  false, false, EC_HVC, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = {
+    4, 4, 4, 4, true,  false, false, EC_HVC
+);
+template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals(
     "Prefetch Abort",        0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-    4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = {
+    4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals(
     "Data Abort",            0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-    8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = {
+    8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals(
     "Virtual Data Abort",    0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-    8, 8, 0, 0, true,  true,  false, EC_INVALID, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = {
+    8, 8, 0, 0, true,  true,  false, EC_INVALID
+);
+template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals(
     // @todo: double check these values
     "Hypervisor Trap",       0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
-    0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = {
+    0, 0, 0, 0, false, false, false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals(
     "Secure Monitor Trap",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
-    4, 2, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = {
+    4, 2, 0, 0, false, false, false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals(
     "IRQ",                   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
-    4, 4, 0, 0, false, true,  false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = {
+    4, 4, 0, 0, false, true,  false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals(
     "Virtual IRQ",           0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
-    4, 4, 0, 0, false, true,  false, EC_INVALID, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = {
+    4, 4, 0, 0, false, true,  false, EC_INVALID
+);
+template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals(
     "FIQ",                   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
-    4, 4, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = {
+    4, 4, 0, 0, false, true,  true,  EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals(
     "Virtual FIQ",           0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
-    4, 4, 0, 0, false, true,  true,  EC_INVALID, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = {
+    4, 4, 0, 0, false, true,  true,  EC_INVALID
+);
+template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals(
     // Some dummy values (SupervisorTrap is AArch64-only)
     "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = {
+    0, 0, 0, 0, false, false, false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals(
     // Some dummy values (PCAlignmentFault is AArch64-only)
     "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = {
+    0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
+);
+template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals(
     // Some dummy values (SPAlignmentFault is AArch64-only)
     "SP Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = {
+    0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
+);
+template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals(
     // Some dummy values (SError is AArch64-only)
     "SError",                0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
-    0, 0, 0, 0, false, true,  true,  EC_SERROR, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = {
+    0, 0, 0, 0, false, true,  true,  EC_SERROR
+);
+template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals(
     // Some dummy values (SoftwareBreakpoint is AArch64-only)
     "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = {
+    0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT
+);
+template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals(
     // Some dummy values
     "ArmSev Flush",          0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
-    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = {
+    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals(
     // Some dummy values (SPAlignmentFault is AArch64-only)
     "Illegal Inst Set State Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-    0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat()
-};
+    0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
+);
 
 Addr
 ArmFault::getVector(ThreadContext *tc)
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6ae4c067e9..d99116fb94 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -171,6 +171,22 @@ class ArmFault : public FaultBase
         const ExceptionClass ec;
 
         FaultStat count;
+        FaultVals(const FaultName& name_, const FaultOffset& offset_,
+                const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
+                const uint16_t& lowerEL64Offset_,
+                const uint16_t& lowerEL32Offset_,
+                const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
+                const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
+                const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
+                const bool& abortDisable_, const bool& fiqDisable_,
+                const ExceptionClass& ec_)
+        : name(name_), offset(offset_), currELTOffset(currELTOffset_),
+          currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
+          lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
+          armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
+          armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
+          hypTrappable(hypTrappable_), abortDisable(abortDisable_),
+          fiqDisable(fiqDisable_), ec(ec_) {}
     };
 
     ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 0f042b4ae3..c5263cf58a 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -51,227 +51,227 @@ namespace SparcISA
 {
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<PowerOnReset>::vals =
-{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()};
+    SparcFault<PowerOnReset>::vals
+("power_on_reset", 0x001, 0, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<WatchDogReset>::vals =
-{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()};
+    SparcFault<WatchDogReset>::vals
+("watch_dog_reset", 0x002, 120, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<ExternallyInitiatedReset>::vals =
-{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()};
+    SparcFault<ExternallyInitiatedReset>::vals
+("externally_initiated_reset", 0x003, 110, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<SoftwareInitiatedReset>::vals =
-{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()};
+    SparcFault<SoftwareInitiatedReset>::vals
+("software_initiated_reset", 0x004, 130, {SH, SH, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<REDStateException>::vals =
-{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()};
+    SparcFault<REDStateException>::vals
+("RED_state_exception", 0x005, 1, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<StoreError>::vals =
-{"store_error", 0x007, 201, {H, H, H}, FaultStat()};
+    SparcFault<StoreError>::vals
+("store_error", 0x007, 201, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionAccessException>::vals =
-{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()};
+    SparcFault<InstructionAccessException>::vals
+("instruction_access_exception", 0x008, 300, {H, H, H});
 
 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionAccessMMUMiss>::vals =
+    SparcFault<InstructionAccessMMUMiss>::vals
     {"inst_mmu", 0x009, 2, {H, H, H}};*/
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionAccessError>::vals =
-{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()};
+    SparcFault<InstructionAccessError>::vals
+("instruction_access_error", 0x00A, 400, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<IllegalInstruction>::vals =
-{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()};
+    SparcFault<IllegalInstruction>::vals
+("illegal_instruction", 0x010, 620, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<PrivilegedOpcode>::vals =
-{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()};
+    SparcFault<PrivilegedOpcode>::vals
+("privileged_opcode", 0x011, 700, {P, SH, SH});
 
 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
-    SparcFault<UnimplementedLDD>::vals =
+    SparcFault<UnimplementedLDD>::vals
     {"unimp_ldd", 0x012, 6, {H, H, H}};*/
 
 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
-    SparcFault<UnimplementedSTD>::vals =
+    SparcFault<UnimplementedSTD>::vals
     {"unimp_std", 0x013, 6, {H, H, H}};*/
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FpDisabled>::vals =
-{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+    SparcFault<FpDisabled>::vals
+("fp_disabled", 0x020, 800, {P, P, H});
 
 /* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
  * as a separate part. Therefore, we use the same code and TT */
 template<> SparcFaultBase::FaultVals
     SparcFault<VecDisabled>::vals =
-{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+{"fp_disabled", 0x020, 800, {P, P, H}};
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FpExceptionIEEE754>::vals =
-{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};
+    SparcFault<FpExceptionIEEE754>::vals
+("fp_exception_ieee_754", 0x021, 1110, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FpExceptionOther>::vals =
-{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()};
+    SparcFault<FpExceptionOther>::vals
+("fp_exception_other", 0x022, 1110, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<TagOverflow>::vals =
-{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()};
+    SparcFault<TagOverflow>::vals
+("tag_overflow", 0x023, 1400, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<CleanWindow>::vals =
-{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()};
+    SparcFault<CleanWindow>::vals
+("clean_window", 0x024, 1010, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DivisionByZero>::vals =
-{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()};
+    SparcFault<DivisionByZero>::vals
+("division_by_zero", 0x028, 1500, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InternalProcessorError>::vals =
-{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()};
+    SparcFault<InternalProcessorError>::vals
+("internal_processor_error", 0x029, 4, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionInvalidTSBEntry>::vals =
-{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()};
+    SparcFault<InstructionInvalidTSBEntry>::vals
+("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DataInvalidTSBEntry>::vals =
-{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()};
+    SparcFault<DataInvalidTSBEntry>::vals
+("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DataAccessException>::vals =
-{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()};
+    SparcFault<DataAccessException>::vals
+("data_access_exception", 0x030, 1201, {H, H, H});
 
 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
-    SparcFault<DataAccessMMUMiss>::vals =
+    SparcFault<DataAccessMMUMiss>::vals
     {"data_mmu", 0x031, 12, {H, H, H}};*/
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DataAccessError>::vals =
-{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()};
+    SparcFault<DataAccessError>::vals
+("data_access_error", 0x032, 1210, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DataAccessProtection>::vals =
-{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()};
+    SparcFault<DataAccessProtection>::vals
+("data_access_protection", 0x033, 1207, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<MemAddressNotAligned>::vals =
-{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()};
+    SparcFault<MemAddressNotAligned>::vals
+("mem_address_not_aligned", 0x034, 1020, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<LDDFMemAddressNotAligned>::vals =
-{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()};
+    SparcFault<LDDFMemAddressNotAligned>::vals
+("LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<STDFMemAddressNotAligned>::vals =
-{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()};
+    SparcFault<STDFMemAddressNotAligned>::vals
+("STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<PrivilegedAction>::vals =
-{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()};
+    SparcFault<PrivilegedAction>::vals
+("privileged_action", 0x037, 1110, {H, H, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<LDQFMemAddressNotAligned>::vals =
-{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()};
+    SparcFault<LDQFMemAddressNotAligned>::vals
+("LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<STQFMemAddressNotAligned>::vals =
-{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()};
+    SparcFault<STQFMemAddressNotAligned>::vals
+("STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionRealTranslationMiss>::vals =
-{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()};
+    SparcFault<InstructionRealTranslationMiss>::vals
+("instruction_real_translation_miss", 0x03E, 208, {H, H, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DataRealTranslationMiss>::vals =
-{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()};
+    SparcFault<DataRealTranslationMiss>::vals
+("data_real_translation_miss", 0x03F, 1203, {H, H, H});
 
 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
-    SparcFault<AsyncDataError>::vals =
+    SparcFault<AsyncDataError>::vals
     {"async_data", 0x040, 2, {H, H, H}};*/
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InterruptLevelN>::vals =
-{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()};
+    SparcFault<InterruptLevelN>::vals
+("interrupt_level_n", 0x040, 0, {P, P, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<HstickMatch>::vals =
-{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()};
+    SparcFault<HstickMatch>::vals
+("hstick_match", 0x05E, 1601, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<TrapLevelZero>::vals =
-{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()};
+    SparcFault<TrapLevelZero>::vals
+("trap_level_zero", 0x05F, 202, {H, H, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InterruptVector>::vals =
-{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()};
+    SparcFault<InterruptVector>::vals
+("interrupt_vector", 0x060, 2630, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<PAWatchpoint>::vals =
-{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()};
+    SparcFault<PAWatchpoint>::vals
+("PA_watchpoint", 0x061, 1209, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<VAWatchpoint>::vals =
-{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()};
+    SparcFault<VAWatchpoint>::vals
+("VA_watchpoint", 0x062, 1120, {P, P, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FastInstructionAccessMMUMiss>::vals =
-{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()};
+    SparcFault<FastInstructionAccessMMUMiss>::vals
+("fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FastDataAccessMMUMiss>::vals =
-{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()};
+    SparcFault<FastDataAccessMMUMiss>::vals
+("fast_data_access_MMU_miss", 0x068, 1203, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FastDataAccessProtection>::vals =
-{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()};
+    SparcFault<FastDataAccessProtection>::vals
+("fast_data_access_protection", 0x06C, 1207, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<InstructionBreakpoint>::vals =
-{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()};
+    SparcFault<InstructionBreakpoint>::vals
+("instruction_break", 0x076, 610, {H, H, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<CpuMondo>::vals =
-{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()};
+    SparcFault<CpuMondo>::vals
+("cpu_mondo", 0x07C, 1608, {P, P, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<DevMondo>::vals =
-{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()};
+    SparcFault<DevMondo>::vals
+("dev_mondo", 0x07D, 1611, {P, P, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<ResumableError>::vals =
-{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()};
+    SparcFault<ResumableError>::vals
+("resume_error", 0x07E, 3330, {P, P, SH});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<SpillNNormal>::vals =
-{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()};
+    SparcFault<SpillNNormal>::vals
+("spill_n_normal", 0x080, 900, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<SpillNOther>::vals =
-{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()};
+    SparcFault<SpillNOther>::vals
+("spill_n_other", 0x0A0, 900, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FillNNormal>::vals =
-{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()};
+    SparcFault<FillNNormal>::vals
+("fill_n_normal", 0x0C0, 900, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<FillNOther>::vals =
-{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()};
+    SparcFault<FillNOther>::vals
+("fill_n_other", 0x0E0, 900, {P, P, H});
 
 template<> SparcFaultBase::FaultVals
-    SparcFault<TrapInstruction>::vals =
-{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()};
+    SparcFault<TrapInstruction>::vals
+("trap_instruction", 0x100, 1602, {P, P, H});
 
 /**
  * This causes the thread context to enter RED state. This causes the side
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 86f8c5b7d1..88826bf614 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -57,13 +57,19 @@ class SparcFaultBase : public FaultBase
         SH = -1,
         ShouldntHappen = SH
     };
+    using PrivilegeLevelSpec = std::array<PrivilegeLevel, NumLevels>;
     struct FaultVals
     {
         const FaultName name;
         const TrapType trapType;
         const FaultPriority priority;
-        const PrivilegeLevel nextPrivilegeLevel[NumLevels];
+        const PrivilegeLevelSpec nextPrivilegeLevel;
         FaultStat count;
+        FaultVals(const FaultName& name_, const TrapType& trapType_,
+                const FaultPriority& priority_, const PrivilegeLevelSpec& il)
+            : name(name_), trapType(trapType_), priority(priority_),
+            nextPrivilegeLevel(il)
+        {}
     };
     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
                 StaticInst::nullStaticInstPtr);
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index d0f77297a7..3e1758ab83 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -232,7 +232,7 @@ class DataWrap : public InfoAccess
     /**
      * Copy constructor, copies are not allowed.
      */
-    DataWrap(const DataWrap &stat) {}
+    DataWrap(const DataWrap &stat) = delete;
 
     /**
      * Can't copy stats.