diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 41e410bd87..e8aeddc92c 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -344,8 +344,6 @@ class VecRegOperand(Operand):
         c_src = ''
         c_dest = ''
 
-        numAccessNeeded = 1
-
         if self.is_src:
             c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec)
 
@@ -474,8 +472,6 @@ class VecElemOperand(Operand):
         c_src = ''
         c_dest = ''
 
-        numAccessNeeded = 1
-
         if self.is_src:
             c_src = ('\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));' %
                     (self.reg_class, self.reg_spec))