From b9a19625cec46fc2dcabfeb362d6f3e5db859e60 Mon Sep 17 00:00:00 2001 From: Erin Le Date: Tue, 22 Oct 2024 14:49:21 -0700 Subject: [PATCH 1/3] stdlib: add SE mode to X86Board This commit adds SE mode to X86Board. X86DemoBoard was also modified, as functions that were previously needed to add SE mode to X86DemoBoard were removed. --- .../gem5/components/boards/x86_board.py | 50 +++++++++++------ .../gem5/prebuilt/demo/x86_demo_board.py | 53 +------------------ 2 files changed, 36 insertions(+), 67 deletions(-) diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index f453c49c24..eb2cbaa942 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -56,6 +56,7 @@ from m5.objects import ( ) from m5.util.convert import toMemorySize +from ...components.boards.se_binary_workload import SEBinaryWorkload from ...isas import ISA from ...resources.resource import AbstractResource from ...utils.override import overrides @@ -66,7 +67,7 @@ from .abstract_system_board import AbstractSystemBoard from .kernel_disk_workload import KernelDiskWorkload -class X86Board(AbstractSystemBoard, KernelDiskWorkload): +class X86Board(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): """ A board capable of full system simulation for X86. @@ -97,17 +98,18 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload): @overrides(AbstractSystemBoard) def _setup_board(self) -> None: - self.pc = Pc() + if self.is_fullsystem(): + self.pc = Pc() - self.workload = X86FsLinux() + self.workload = X86FsLinux() - # North Bridge - self.iobus = IOXBar() + # North Bridge + self.iobus = IOXBar() - # Set up all of the I/O. - self._setup_io_devices() + # Set up all of the I/O. + self._setup_io_devices() - self.m5ops_base = 0xFFFF0000 + self.m5ops_base = 0xFFFF0000 def _setup_io_devices(self): """Sets up the x86 IO devices. @@ -291,27 +293,45 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload): @overrides(AbstractSystemBoard) def has_io_bus(self) -> bool: - return True + return self.is_fullsystem() @overrides(AbstractSystemBoard) - def get_io_bus(self) -> BaseXBar: - return self.iobus + def get_io_bus(self) -> IOXBar: + if self.has_io_bus(): + return self.iobus + else: + raise NotImplementedError( + "Board was not configured for FS mode and does not have an " + "I/O bus. Use `has_io_bus()` to check this." + ) @overrides(AbstractSystemBoard) def has_dma_ports(self) -> bool: - return True + return self.is_fullsystem() @overrides(AbstractSystemBoard) def get_dma_ports(self) -> Sequence[Port]: - return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports] + if self.has_dma_ports(): + return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports] + else: + raise NotImplementedError( + "Board was not configured for FS mode and does not have DMA " + "ports. Use `has_dma_ports()` to check this." + ) @overrides(AbstractSystemBoard) def has_coherent_io(self) -> bool: - return True + return self.is_fullsystem() @overrides(AbstractSystemBoard) def get_mem_side_coherent_io_port(self) -> Port: - return self.iobus.mem_side_ports + if self.has_coherent_io(): + return self.iobus.mem_side_ports + else: + raise NotImplementedError( + "Board was not configured for FS mode and does not have I/O " + "ports. Use has_coherent_io to check this." + ) @overrides(AbstractSystemBoard) def _setup_memory_ranges(self): diff --git a/src/python/gem5/prebuilt/demo/x86_demo_board.py b/src/python/gem5/prebuilt/demo/x86_demo_board.py index ac89847f2b..9bed54623e 100644 --- a/src/python/gem5/prebuilt/demo/x86_demo_board.py +++ b/src/python/gem5/prebuilt/demo/x86_demo_board.py @@ -24,15 +24,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import ( - IOXBar, - Pc, - Port, - X86FsLinux, -) from m5.util import warn -from ...components.boards.se_binary_workload import SEBinaryWorkload from ...components.boards.x86_board import X86Board from ...components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( PrivateL1SharedL2CacheHierarchy, @@ -41,11 +34,10 @@ from ...components.memory.multi_channel import DualChannelDDR4_2400 from ...components.processors.cpu_types import CPUTypes from ...components.processors.simple_processor import SimpleProcessor from ...isas import ISA -from ...utils.override import overrides from ...utils.requires import requires -class X86DemoBoard(X86Board, SEBinaryWorkload): +class X86DemoBoard(X86Board): """ This prebuilt X86 board is used for demonstration purposes. It simulates an X86 3GHz dual-core system with a 3GiB DDR4_2400 memory system. The @@ -99,46 +91,3 @@ class X86DemoBoard(X86Board, SEBinaryWorkload): memory=memory, cache_hierarchy=cache_hierarchy, ) - - @overrides(X86Board) - def _setup_board(self) -> None: - if self._is_fs: - self.pc = Pc() - - self.workload = X86FsLinux() - - # North Bridge - self.iobus = IOXBar() - - # Set up all of the I/O. - self._setup_io_devices() - - self.m5ops_base = 0xFFFF0000 - - @overrides(X86Board) - def has_io_bus(self) -> bool: - return self.is_fullsystem() - - @overrides(X86Board) - def get_io_bus(self) -> IOXBar: - if self.has_io_bus(): - return self.iobus - else: - raise NotImplementedError( - "X86DemoBoard does not have an IO bus. " - "Use `has_io_bus()` to check this." - ) - - @overrides(X86Board) - def has_coherent_io(self) -> bool: - return self.is_fullsystem() - - @overrides(X86Board) - def get_mem_side_coherent_io_port(self) -> Port: - if self.has_coherent_io(): - return self.iobus.mem_side_ports - else: - raise NotImplementedError( - "x86DemoBoard does not have any I/O ports. Use has_coherent_io" - " to check this." - ) From 7b7f5ef34a6ddd027c27f3f35474505c8b8498aa Mon Sep 17 00:00:00 2001 From: Erin Le Date: Tue, 22 Oct 2024 16:31:01 -0700 Subject: [PATCH 2/3] stdlib: add SE mode to RiscvBoard This commit adds SE mode to RiscvBoard. RiscvDemoBoard has also been modified as adding SE mode to RiscvBoard made the overridden functions in RiscvDemoBoard obsolete. --- .../gem5/components/boards/riscv_board.py | 101 ++++++++++------- .../gem5/prebuilt/demo/riscv_demo_board.py | 103 +----------------- 2 files changed, 61 insertions(+), 143 deletions(-) diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index cbbde80a71..e71015c046 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -60,6 +60,7 @@ from m5.util.fdthelper import ( FdtState, ) +from ...components.boards.se_binary_workload import SEBinaryWorkload from ...isas import ISA from ...resources.resource import AbstractResource from ...utils.override import overrides @@ -70,7 +71,7 @@ from .abstract_system_board import AbstractSystemBoard from .kernel_disk_workload import KernelDiskWorkload -class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): +class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): """ A board capable of full system simulation for RISC-V. @@ -100,47 +101,53 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): @overrides(AbstractSystemBoard) def _setup_board(self) -> None: - self.workload = RiscvBootloaderKernelWorkload() + if self.is_fullsystem(): + self.workload = RiscvBootloaderKernelWorkload() - # Contains a CLINT, PLIC, UART, and some functions for the dtb, etc. - self.platform = HiFive() - # Note: This only works with single threaded cores. - self.platform.plic.hart_config = ",".join( - ["MS" for _ in range(self.processor.get_num_cores())] - ) - self.platform.attachPlic() - self.platform.clint.num_threads = self.processor.get_num_cores() + # Contains a CLINT, PLIC, UART, and some functions for the dtb, etc. + self.platform = HiFive() + # Note: This only works with single threaded cores. + self.platform.plic.hart_config = ",".join( + ["MS" for _ in range(self.processor.get_num_cores())] + ) + self.platform.attachPlic() + self.platform.clint.num_threads = self.processor.get_num_cores() - # Add the RTC - # TODO: Why 100MHz? Does something else need to change when this does? - self.platform.rtc = RiscvRTC(frequency=Frequency("100MHz")) - self.platform.clint.int_pin = self.platform.rtc.int_pin + # Add the RTC + # TODO: Why 100MHz? Does something else need to change when this does? + self.platform.rtc = RiscvRTC( + frequency=Frequency("100MHz") + ) # page 77, section 7.1 + self.platform.clint.int_pin = self.platform.rtc.int_pin - # Incoherent I/O bus - self.iobus = IOXBar() - self.iobus.badaddr_responder = BadAddr() - self.iobus.default = self.iobus.badaddr_responder.pio + # Incoherent I/O bus + self.iobus = IOXBar() + self.iobus.badaddr_responder = BadAddr() + self.iobus.default = self.iobus.badaddr_responder.pio - # The virtio disk - self.disk = RiscvMmioVirtIO( - vio=VirtIOBlock(), - interrupt_id=0x8, - pio_size=4096, - pio_addr=0x10008000, - ) + # The virtio disk + self.disk = RiscvMmioVirtIO( + vio=VirtIOBlock(), + interrupt_id=0x8, + pio_size=4096, + pio_addr=0x10008000, + ) - # The virtio rng - self.rng = RiscvMmioVirtIO( - vio=VirtIORng(), - interrupt_id=0x8, - pio_size=4096, - pio_addr=0x10007000, - ) + # The virtio rng + self.rng = RiscvMmioVirtIO( + vio=VirtIORng(), + interrupt_id=0x8, + pio_size=4096, + pio_addr=0x10007000, + ) - # Note: This overrides the platform's code because the platform isn't - # general enough. - self._on_chip_devices = [self.platform.clint, self.platform.plic] - self._off_chip_devices = [self.platform.uart, self.disk, self.rng] + # Note: This overrides the platform's code because the platform + # isn't general enough. + self._on_chip_devices = [self.platform.clint, self.platform.plic] + self._off_chip_devices = [self.platform.uart, self.disk, self.rng] + + else: + pass def _setup_io_devices(self) -> None: """Connect the I/O devices to the I/O bus.""" @@ -213,19 +220,31 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): @overrides(AbstractSystemBoard) def has_io_bus(self) -> bool: - return True + return self.is_fullsystem() @overrides(AbstractSystemBoard) def get_io_bus(self) -> IOXBar: - return self.iobus + if self.has_io_bus(): + return self.iobus + else: + raise NotImplementedError( + "Board was not configured for FS mode and does not have an " + "I/O bus. Use `has_io_bus()` to check this." + ) @overrides(AbstractSystemBoard) def has_coherent_io(self) -> bool: - return True + return self.is_fullsystem() @overrides(AbstractSystemBoard) def get_mem_side_coherent_io_port(self) -> Port: - return self.iobus.mem_side_ports + if self.has_coherent_io(): + return self.iobus.mem_side_ports + else: + raise NotImplementedError( + "Board was not configured for FS mode and does not have any " + "I/O ports. Use has_coherent_io to check this." + ) @overrides(AbstractSystemBoard) def _setup_memory_ranges(self): @@ -509,7 +528,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): # # This should be refactored in the future as part of a chance to have # all boards support both FS and SE modes. - if self._is_fs: + if self.is_fullsystem(): if len(self._bootloader) > 0: self.workload.bootloader_addr = 0x0 self.workload.bootloader_filename = self._bootloader[0] diff --git a/src/python/gem5/prebuilt/demo/riscv_demo_board.py b/src/python/gem5/prebuilt/demo/riscv_demo_board.py index 4bffc11a66..fc0951e73a 100644 --- a/src/python/gem5/prebuilt/demo/riscv_demo_board.py +++ b/src/python/gem5/prebuilt/demo/riscv_demo_board.py @@ -24,30 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import m5 -from m5.objects import ( - AddrRange, - BadAddr, - Bridge, - CowDiskImage, - Frequency, - GenericRiscvPciHost, - HiFive, - IGbE_e1000, - IOXBar, - PMAChecker, - Port, - RawDiskImage, - RiscvBootloaderKernelWorkload, - RiscvMmioVirtIO, - RiscvRTC, - VirtIOBlock, - VirtIORng, -) from m5.util import warn from ...components.boards.riscv_board import RiscvBoard -from ...components.boards.se_binary_workload import SEBinaryWorkload from ...components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import ( PrivateL1SharedL2CacheHierarchy, ) @@ -60,7 +39,7 @@ from ...utils.override import overrides from ...utils.requires import requires -class RiscvDemoBoard(RiscvBoard, SEBinaryWorkload): +class RiscvDemoBoard(RiscvBoard): """ This board is based on the X86DemoBoard. @@ -106,83 +85,3 @@ class RiscvDemoBoard(RiscvBoard, SEBinaryWorkload): memory=memory, cache_hierarchy=cache_hierarchy, ) - - # Taken from Riscv Matched board. Below are functions that are needed to - # get SE mode to work. - - @overrides(RiscvBoard) - def _setup_board(self) -> None: - if self._is_fs: - self.workload = RiscvBootloaderKernelWorkload() - - # Contains a CLINT, PLIC, UART, and some functions for the dtb, etc. - self.platform = HiFive() - # Note: This only works with single threaded cores. - self.platform.plic.hart_config = ",".join( - ["MS" for _ in range(self.processor.get_num_cores())] - ) - self.platform.attachPlic() - self.platform.clint.num_threads = self.processor.get_num_cores() - - # Add the RTC - self.platform.rtc = RiscvRTC( - frequency=Frequency("100MHz") - ) # page 77, section 7.1 - self.platform.clint.int_pin = self.platform.rtc.int_pin - - # Incoherent I/O bus - self.iobus = IOXBar() - self.iobus.badaddr_responder = BadAddr() - self.iobus.default = self.iobus.badaddr_responder.pio - - # The virtio disk - self.disk = RiscvMmioVirtIO( - vio=VirtIOBlock(), - interrupt_id=0x8, - pio_size=4096, - pio_addr=0x10008000, - ) - - # The virtio rng - self.rng = RiscvMmioVirtIO( - vio=VirtIORng(), - interrupt_id=0x8, - pio_size=4096, - pio_addr=0x10007000, - ) - - # Note: This overrides the platform's code because the platform isn't - # general enough. - self._on_chip_devices = [self.platform.clint, self.platform.plic] - self._off_chip_devices = [self.platform.uart, self.disk, self.rng] - - else: - pass - - @overrides(RiscvBoard) - def has_io_bus(self) -> bool: - return self._is_fs - - @overrides(RiscvBoard) - def get_io_bus(self) -> IOXBar: - if self.has_io_bus(): - return self.iobus - else: - raise NotImplementedError( - "RiscvDemoBoard does not have an IO bus. " - "Use `has_io_bus()` to check this." - ) - - @overrides(RiscvBoard) - def has_coherent_io(self) -> bool: - return self._is_fs - - @overrides(RiscvBoard) - def get_mem_side_coherent_io_port(self) -> Port: - if self.has_coherent_io(): - return self.iobus.mem_side_ports - else: - raise NotImplementedError( - "RiscvDemoBoard does not have any I/O ports. Use has_coherent_io to " - "check this." - ) From 11dd2c6c0980f3ededd796aa1e9bad1be9dbfe71 Mon Sep 17 00:00:00 2001 From: Erin Le Date: Mon, 28 Oct 2024 15:00:19 -0700 Subject: [PATCH 3/3] stdlib: address requested changes to X86, Riscv boards This commit addresses the requested changes. An additional comment is added for clarification, the exception type is changed, and a few of the error messages have been modified. --- .../gem5/components/boards/riscv_board.py | 20 ++++++++++--------- .../gem5/components/boards/x86_board.py | 19 +++++++++--------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index e71015c046..5c3eb187bd 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -147,6 +147,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): self._off_chip_devices = [self.platform.uart, self.disk, self.rng] else: + # SE mode board setup pass def _setup_io_devices(self) -> None: @@ -213,9 +214,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): @overrides(AbstractSystemBoard) def get_dma_ports(self) -> List[Port]: - raise NotImplementedError( - "RISCVBoard does not have DMA Ports. " - "Use `has_dma_ports()` to check this." + raise Exception( + "Cannot execute `get_dma_ports()`: Board does not have DMA ports " + "to return. Use `has_dma_ports()` to check this." ) @overrides(AbstractSystemBoard) @@ -227,9 +228,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): if self.has_io_bus(): return self.iobus else: - raise NotImplementedError( - "Board was not configured for FS mode and does not have an " - "I/O bus. Use `has_io_bus()` to check this." + raise Exception( + "Cannot execute `get_io_bus()`: Board does not have an I/O " + "bus to return. Use `has_io_bus()` to check this." ) @overrides(AbstractSystemBoard) @@ -241,9 +242,10 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): if self.has_coherent_io(): return self.iobus.mem_side_ports else: - raise NotImplementedError( - "Board was not configured for FS mode and does not have any " - "I/O ports. Use has_coherent_io to check this." + raise Exception( + "Cannot execute `get_mem_side_coherent_io_port()`: Board does " + "not have any I/O ports to return. Use `has_coherent_io()` to " + "check this." ) @overrides(AbstractSystemBoard) diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index eb2cbaa942..557c96881e 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -300,9 +300,9 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): if self.has_io_bus(): return self.iobus else: - raise NotImplementedError( - "Board was not configured for FS mode and does not have an " - "I/O bus. Use `has_io_bus()` to check this." + raise Exception( + "Cannot execute `get_io_bus()`: Board does not have an I/O " + "bus to return. Use `has_io_bus()` to check this." ) @overrides(AbstractSystemBoard) @@ -314,9 +314,9 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): if self.has_dma_ports(): return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports] else: - raise NotImplementedError( - "Board was not configured for FS mode and does not have DMA " - "ports. Use `has_dma_ports()` to check this." + raise Exception( + "Cannot execute `get_dma_ports()`: Board does not have DMA " + "ports to return. Use `has_dma_ports()` to check this." ) @overrides(AbstractSystemBoard) @@ -328,9 +328,10 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload): if self.has_coherent_io(): return self.iobus.mem_side_ports else: - raise NotImplementedError( - "Board was not configured for FS mode and does not have I/O " - "ports. Use has_coherent_io to check this." + raise Exception( + "Cannot execute `get_mem_side_coherent_io_port()`: Board does " + "not have I/O ports to return. Use `has_coherent_io()` to " + "check this." ) @overrides(AbstractSystemBoard)