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cpu: add a condition-code register class

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Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
This commit is contained in:
Yasuko Eckert
2013-10-15 14:22:44 -04:00
parent 5526221847
commit 2c293823aa
57 changed files with 806 additions and 36 deletions
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3
src/arch/SConscript
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@@ -135,5 +135,6 @@ env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
DebugFlag('CCRegs')
DebugFlag('MiscRegs')
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])