From 2c229aa2ff0a24db4b6b9581dc64ed070e8aff1f Mon Sep 17 00:00:00 2001 From: Kaustav Goswami Date: Wed, 25 Oct 2023 13:59:51 -0700 Subject: [PATCH] configs,ext: gem5 SST bridge calls m5.instantiate() in gem5 This change updates the gem5 SST bridge to call m5.instantiate() in the gem5 config script instead of in the SST component. This allows more flexibility for the gem5-SST setup, as we can now write traffic generators using the bridge. Change-Id: I510a8c15f8fb00bdbdd60dafa2d9f5ad011e48f2 Signed-off-by: Kaustav Goswami --- configs/example/sst/arm_fs.py | 1 + configs/example/sst/riscv_fs.py | 1 + ext/sst/gem5.cc | 8 +------- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/configs/example/sst/arm_fs.py b/configs/example/sst/arm_fs.py index 14dd7c4743..b8fcb68e37 100644 --- a/configs/example/sst/arm_fs.py +++ b/configs/example/sst/arm_fs.py @@ -185,3 +185,4 @@ for cpu in system.cpu: cpu.createInterruptController() root = Root(full_system=True, system=system) +m5.instantiate() diff --git a/configs/example/sst/riscv_fs.py b/configs/example/sst/riscv_fs.py index 46754debf5..c82ad9a6b9 100644 --- a/configs/example/sst/riscv_fs.py +++ b/configs/example/sst/riscv_fs.py @@ -175,3 +175,4 @@ for cpu in system.cpu: cpu.createInterruptController() root = Root(full_system=True, system=system) +m5.instantiate() diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc index 8c845f329e..3ea6127ecd 100644 --- a/ext/sst/gem5.cc +++ b/ext/sst/gem5.cc @@ -204,13 +204,7 @@ gem5Component::init(unsigned phase) if (phase == 0) { initPython(args.size(), &args[0]); - - const std::vector m5_instantiate_commands = { - "import m5", - "m5.instantiate()" - }; - execPythonCommands(m5_instantiate_commands); - + // m5.instantiate() was moved to the gem5 script. // calling SimObject.startup() const std::vector simobject_setup_commands = { "import atexit",