misc: Run pre-commit run on all files in repo

The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/python/gem5/components/boards/x86_board.py

@@ -105,7 +105,7 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
         self.m5ops_base = 0xFFFF0000
 
     def _setup_io_devices(self):
-        """ Sets up the x86 IO devices.
+        """Sets up the x86 IO devices.
 
         Note: This is mostly copy-paste from prior X86 FS setups. Some of it
         may not be documented and there may be bugs.

src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py

@@ -38,8 +38,7 @@ from .abstract_node import TriggerMessageBuffer
 
 
 class MemoryController(Memory_Controller):
-    """A controller that connects to memory
-    """
+    """A controller that connects to memory"""
 
     _version = 0
 

src/python/gem5/components/memory/dramsim_3.py

@@ -128,7 +128,9 @@ class SingleChannel(AbstractMemorySystem):
         self.mem_ctrl.range = ranges[0]
 
 
-def SingleChannelDDR3_1600(size: Optional[str] = "2048MB",) -> SingleChannel:
+def SingleChannelDDR3_1600(
+    size: Optional[str] = "2048MB",
+) -> SingleChannel:
     """
     A single channel DDR3_1600.
 

src/python/gem5/components/memory/memory.py

@@ -45,7 +45,7 @@ def _try_convert(val, cls):
 
 def _isPow2(num):
     log_num = int(log(num, 2))
-    if 2 ** log_num != num:
+    if 2**log_num != num:
         return False
     else:
         return True

src/python/gem5/components/memory/multi_channel.py

@@ -34,21 +34,27 @@ from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
 from .dram_interfaces.hbm import HBM_1000_4H_1x64
 
 
-def DualChannelDDR3_1600(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR3_1600(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR3_1600_8x8 based DIMM
     """
     return ChanneledMemory(DDR3_1600_8x8, 2, 64, size=size)
 
 
-def DualChannelDDR3_2133(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR3_2133(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR3_2133_8x8 based DIMM
     """
     return ChanneledMemory(DDR3_2133_8x8, 2, 64, size=size)
 
 
-def DualChannelDDR4_2400(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR4_2400(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR4_2400_8x8 based DIMM
     """
@@ -61,7 +67,9 @@ def DualChannelLPDDR3_1600(
     return ChanneledMemory(LPDDR3_1600_1x32, 2, 64, size=size)
 
 
-def HBM2Stack(size: Optional[str] = None,) -> AbstractMemorySystem:
+def HBM2Stack(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     if not size:
         size = "4GiB"
     return ChanneledMemory(HBM_1000_4H_1x64, 16, 64, size=size)

src/python/gem5/components/memory/single_channel.py

@@ -68,7 +68,9 @@ def SingleChannelLPDDR3_1600(
     return ChanneledMemory(LPDDR3_1600_1x32, 1, 64, size=size)
 
 
-def SingleChannelHBM(size: Optional[str] = None,) -> AbstractMemorySystem:
+def SingleChannelHBM(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     if not size:
         size = "256MiB"
     return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size)

src/python/gem5/components/processors/simple_switchable_processor.py

@@ -52,9 +52,9 @@ class SimpleSwitchableProcessor(SwitchableProcessor):
         isa: Optional[ISA] = None,
     ) -> None:
         """
-        param starting_core_type: The CPU type for each type in the processor
+        :param starting_core_type: The CPU type for each type in the processor
         to start with (i.e., when the simulation has just started).
-:
+
         :param switch_core_types: The CPU type for each core, to be switched
         to..
 

src/python/m5/params.py

@@ -594,7 +594,7 @@ class CheckedIntType(MetaParamValue):
                 )
             if cls.unsigned:
                 cls.min = 0
-                cls.max = 2 ** cls.size - 1
+                cls.max = 2**cls.size - 1
             else:
                 cls.min = -(2 ** (cls.size - 1))
                 cls.max = (2 ** (cls.size - 1)) - 1

src/python/m5/simulate.py

@@ -58,7 +58,7 @@ from .util import fatal
 from .util import attrdict
 
 # define a MaxTick parameter, unsigned 64 bit
-MaxTick = 2 ** 64 - 1
+MaxTick = 2**64 - 1
 
 _drain_manager = _m5.drain.DrainManager.instance()
 

src/python/m5/util/terminal.py

@@ -80,7 +80,6 @@ try:
         else:
             return ""
 
-
 except:
     cap_string = null_cap_string