misc: Run pre-commit run on all files in repo
The following command was run: ``` pre-commit run --all-files ``` This ensures all the files in the repository are formatted to pass our checks. Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
committed by
Bobby Bruce
parent
64add0e04d
commit
2bc5a8b71a
@@ -142,13 +142,11 @@ class HiFive(Platform):
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terminal = Terminal()
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def _on_chip_devices(self):
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"""Returns a list of on-chip peripherals
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"""
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"""Returns a list of on-chip peripherals"""
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return [self.clint, self.plic]
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def _off_chip_devices(self):
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"""Returns a list of off-chip peripherals
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"""
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"""Returns a list of off-chip peripherals"""
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devices = [self.uart]
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if hasattr(self, "disk"):
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devices.append(self.disk)
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@@ -158,7 +156,7 @@ class HiFive(Platform):
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def _on_chip_ranges(self):
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"""Returns a list of on-chip peripherals
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address range
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address range
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"""
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return [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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@@ -167,7 +165,7 @@ class HiFive(Platform):
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def _off_chip_ranges(self):
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"""Returns a list of off-chip peripherals
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address range
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address range
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"""
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return [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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@@ -175,8 +173,7 @@ class HiFive(Platform):
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]
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def attachPlic(self):
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"""Count number of PLIC interrupt sources
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"""
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"""Count number of PLIC interrupt sources"""
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plic_srcs = [
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self.uart_int_id,
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self.pci_host.int_base + self.pci_host.int_count,
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@@ -188,21 +185,21 @@ class HiFive(Platform):
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def attachOnChipIO(self, bus):
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"""Attach on-chip IO devices, needs modification
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to support DMA
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to support DMA
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"""
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for device in self._on_chip_devices():
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device.pio = bus.mem_side_ports
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def attachOffChipIO(self, bus):
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"""Attach off-chip IO devices, needs modification
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to support DMA
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to support DMA
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"""
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for device in self._off_chip_devices():
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device.pio = bus.mem_side_ports
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def setNumCores(self, num_cpu):
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""" Sets the PLIC and CLINT to have the right number of threads and
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contexts. Assumes that the cores have a single hardware thread.
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"""Sets the PLIC and CLINT to have the right number of threads and
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contexts. Assumes that the cores have a single hardware thread.
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"""
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self.plic.n_contexts = num_cpu * 2
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self.clint.num_threads = num_cpu
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