misc: Run pre-commit run on all files in repo

The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Bobby R. Bruce
2022-08-22 12:34:19 -07:00
committed by Bobby Bruce
parent 64add0e04d
commit 2bc5a8b71a
181 changed files with 1445 additions and 1229 deletions

View File

@@ -124,4 +124,4 @@ For more detail, please see the following paper:
T. Ta, X. Zhang, A. Gutierrez and B. M. Beckmann, "Autonomous Data-Race-Free
GPU Testing," 2019 IEEE International Symposium on Workload Characterization
(IISWC), Orlando, FL, USA, 2019, pp. 81-92, doi:
10.1109/IISWC47752.2019.9042019.
10.1109/IISWC47752.2019.9042019.

View File

@@ -68,4 +68,3 @@ if env['USE_PYTHON']:
SimObject('TrafficGen.py', sim_objects=['TrafficGen'], tags='protobuf')
Source('trace_gen.cc', tags='protobuf')
Source('traffic_gen.cc', tags='protobuf')

View File

@@ -39,7 +39,7 @@ from m5.objects.BaseCPU import BaseCPU
class TraceCPU(BaseCPU):
"""Trace CPU model which replays traces generated in a prior simulation
using DerivO3CPU or its derived classes. It interfaces with L1 caches.
using DerivO3CPU or its derived classes. It interfaces with L1 caches.
"""
type = "TraceCPU"