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Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults

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--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
This commit is contained in:
Gabe Black
2006-11-01 16:44:45 -05:00
parent f3ba6d20f6
commit 2b11b47357
40 changed files with 317 additions and 254 deletions
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14
src/cpu/thread_context.hh
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@@ -224,11 +224,11 @@ class ThreadContext
virtual MiscReg readMiscReg(int misc_reg) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
@@ -410,13 +410,13 @@ class ProxyThreadContext : public ThreadContext
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{ return actualTC->readMiscRegWithEffect(misc_reg, fault); }
MiscReg readMiscRegWithEffect(int misc_reg)
{ return actualTC->readMiscRegWithEffect(misc_reg); }
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscReg(misc_reg, val); }
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscRegWithEffect(misc_reg, val); }
unsigned readStCondFailures()