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Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults

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--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
This commit is contained in:
Gabe Black
2006-11-01 16:44:45 -05:00
parent f3ba6d20f6
commit 2b11b47357
40 changed files with 317 additions and 254 deletions
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23
src/cpu/checker/cpu.hh
View File

@@ -47,9 +47,12 @@
// forward declarations
#if FULL_SYSTEM
namespace TheISA
{
class ITB;
class DTB;
}
class Processor;
class AlphaITB;
class AlphaDTB;
class PhysicalMemory;
class RemoteGDB;
@@ -96,8 +99,8 @@ class CheckerCPU : public BaseCPU
struct Params : public BaseCPU::Params
{
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
TheISA::ITB *itb;
TheISA::DTB *dtb;
#else
Process *process;
#endif
@@ -140,8 +143,8 @@ class CheckerCPU : public BaseCPU
ThreadContext *tc;
AlphaITB *itb;
AlphaDTB *dtb;
TheISA::ITB *itb;
TheISA::DTB *dtb;
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
@@ -301,19 +304,19 @@ class CheckerCPU : public BaseCPU
return thread->readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return thread->readMiscRegWithEffect(misc_reg, fault);
return thread->readMiscRegWithEffect(misc_reg);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
result.integer = val;
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
miscRegIdxs.push(misc_reg);
return thread->setMiscRegWithEffect(misc_reg, val);

16
src/cpu/checker/thread_context.hh
View File

@@ -87,9 +87,9 @@ class CheckerThreadContext : public ThreadContext
PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
@@ -248,19 +248,19 @@ class CheckerThreadContext : public ThreadContext
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{ return actualTC->readMiscRegWithEffect(misc_reg, fault); }
MiscReg readMiscRegWithEffect(int misc_reg)
{ return actualTC->readMiscRegWithEffect(misc_reg); }
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
checkerTC->setMiscReg(misc_reg, val);
return actualTC->setMiscReg(misc_reg, val);
actualTC->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
checkerTC->setMiscRegWithEffect(misc_reg, val);
return actualTC->setMiscRegWithEffect(misc_reg, val);
actualTC->setMiscRegWithEffect(misc_reg, val);
}
unsigned readStCondFailures()

6
src/cpu/exec_context.hh
View File

@@ -101,14 +101,14 @@ class ExecContext {
/** Reads a miscellaneous register, handling any architectural
* side effects due to reading that register. */
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
MiscReg readMiscRegWithEffect(int misc_reg);
/** Sets a miscellaneous register. */
Fault setMiscReg(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
/** Sets a miscellaneous register, handling any architectural
* side effects due to writing that register. */
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
/** Records the effective address of the instruction. Only valid
* for memory ops. */

16
src/cpu/o3/alpha/cpu.hh
View File

@@ -37,6 +37,12 @@
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
namespace TheISA
{
class ITB;
class DTB;
}
class EndQuiesceEvent;
namespace Kernel {
class Statistics;
@@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU<Impl>
#if FULL_SYSTEM
/** ITB pointer. */
AlphaITB *itb;
AlphaISA::ITB *itb;
/** DTB pointer. */
AlphaDTB *dtb;
AlphaISA::DTB *dtb;
#endif
/** Registers statistics. */
@@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU<Impl>
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of

4
src/cpu/o3/alpha/cpu_builder.cc
View File

@@ -54,8 +54,8 @@ Param<int> activity;
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<AlphaISA::ITB *> itb;
SimObjectParam<AlphaISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectVectorParam<Process *> workload;

13
src/cpu/o3/alpha/cpu_impl.hh
View File

@@ -198,25 +198,24 @@ AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
template <class Impl>
TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
unsigned tid)
AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
}
template <class Impl>
Fault
void
AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
{
return this->regFile.setMiscReg(misc_reg, val, tid);
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
Fault
void
AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
unsigned tid)
{
return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
}
template <class Impl>

9
src/cpu/o3/alpha/dyn_inst.hh
View File

@@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return this->cpu->readMiscRegWithEffect(misc_reg, fault,
this->threadNumber);
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
}
/** Sets a misc. register. */
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
@@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(misc_reg, val,
this->threadNumber);

11
src/cpu/o3/alpha/params.hh
View File

@@ -35,8 +35,11 @@
#include "cpu/o3/params.hh"
//Forward declarations
class AlphaDTB;
class AlphaITB;
namespace AlphaISA
{
class DTB;
class ITB;
}
class MemObject;
class Process;
class System;
@@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params
public:
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
AlphaISA::ITB *itb;
AlphaISA::DTB *dtb;
#endif
};

4
src/cpu/o3/alpha/thread_context.hh
View File

@@ -37,10 +37,10 @@ class AlphaTC : public O3ThreadContext<Impl>
public:
#if FULL_SYSTEM
/** Returns a pointer to the ITB. */
virtual AlphaITB *getITBPtr() { return this->cpu->itb; }
virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; }
/** Returns a pointer to the DTB. */
virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; }
virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; }
/** Returns pointer to the quiesce event. */
virtual EndQuiesceEvent *getQuiesceEvent()

4
src/cpu/o3/checker_builder.cc
View File

@@ -67,8 +67,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
Param<Tick> progress_interval;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;

7
src/cpu/o3/mips/cpu.hh
View File

@@ -92,16 +92,15 @@ class MipsO3CPU : public FullO3CPU<Impl>
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegWithEffect(int misc_reg,
Fault &fault, unsigned tid);
TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
Fault setMiscRegWithEffect(int misc_reg,
void setMiscRegWithEffect(int misc_reg,
const TheISA::MiscReg &val, unsigned tid);
/** Initiates a squash of all in-flight instructions for a given

13
src/cpu/o3/mips/cpu_impl.hh
View File

@@ -156,25 +156,24 @@ MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
template <class Impl>
MiscReg
MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
unsigned tid)
MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
}
template <class Impl>
Fault
void
MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
{
return this->regFile.setMiscReg(misc_reg, val, tid);
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
Fault
void
MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
unsigned tid)
{
return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
}
template <class Impl>

11
src/cpu/o3/mips/dyn_inst.hh
View File

@@ -103,23 +103,22 @@ class MipsDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return this->cpu->readMiscRegWithEffect(misc_reg, fault,
this->threadNumber);
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
}
/** Sets a misc. register. */
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(misc_reg, val,
this->threadNumber);

14
src/cpu/o3/regfile.hh
View File

@@ -37,7 +37,6 @@
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#include "sim/faults.hh"
#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
@@ -232,22 +231,21 @@ class PhysRegFile
return miscRegs[thread_id].readReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
unsigned thread_id)
MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
{
return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
return miscRegs[thread_id].readRegWithEffect(misc_reg,
cpu->tcBase(thread_id));
}
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
{
return miscRegs[thread_id].setReg(misc_reg, val);
miscRegs[thread_id].setReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
unsigned thread_id)
{
return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
miscRegs[thread_id].setRegWithEffect(misc_reg, val,
cpu->tcBase(thread_id));
}

8
src/cpu/o3/thread_context.hh
View File

@@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{ return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
virtual MiscReg readMiscRegWithEffect(int misc_reg)
{ return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
/** Sets a misc. register. */
virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
virtual void setMiscReg(int misc_reg, const MiscReg &val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.

13
src/cpu/o3/thread_context_impl.hh
View File

@@ -439,33 +439,28 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
}
template <class Impl>
Fault
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
cpu->setMiscReg(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
cpu->squashFromTC(thread->readTid());
}
return ret_fault;
}
template <class Impl>
Fault
void
O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
const MiscReg &val)
{
Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
thread->readTid());
cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
cpu->squashFromTC(thread->readTid());
}
return ret_fault;
}
#if !FULL_SYSTEM

4
src/cpu/ozone/checker_builder.cc
View File

@@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
Param<Tick> progress_interval;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;

17
src/cpu/ozone/cpu.hh
View File

@@ -51,8 +51,11 @@
#if FULL_SYSTEM
#include "arch/alpha/tlb.hh"
class AlphaITB;
class AlphaDTB;
namespace TheISA
{
class ITB;
class DTB;
}
class PhysicalMemory;
class MemoryController;
@@ -120,9 +123,9 @@ class OzoneCPU : public BaseCPU
PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
AlphaITB *getITBPtr() { return cpu->itb; }
TheISA::ITB *getITBPtr() { return cpu->itb; }
AlphaDTB * getDTBPtr() { return cpu->dtb; }
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
@@ -224,11 +227,11 @@ class OzoneCPU : public BaseCPU
// ISA stuff:
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
MiscReg readMiscRegWithEffect(int misc_reg);
Fault setMiscReg(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
unsigned readStCondFailures()
{ return thread->storeCondFailures; }

4
src/cpu/ozone/cpu_builder.cc
View File

@@ -61,8 +61,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectVectorParam<Process *> workload;

18
src/cpu/ozone/cpu_impl.hh
View File

@@ -1156,37 +1156,31 @@ OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
template <class Impl>
TheISA::MiscReg
OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
{
return thread->miscRegFile.readRegWithEffect(misc_reg,
fault, this);
return thread->miscRegFile.readRegWithEffect(misc_reg, this);
}
template <class Impl>
Fault
void
OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val);
thread->miscRegFile.setReg(misc_reg, val);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
return ret_fault;
}
template <class Impl>
Fault
void
OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val,
this);
thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
return ret_fault;
}

6
src/cpu/ozone/dyn_inst.hh
View File

@@ -230,11 +230,11 @@ class OzoneDynInst : public BaseDynInst<Impl>
// ISA stuff
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
MiscReg readMiscRegWithEffect(int misc_reg);
Fault setMiscReg(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
Fault hwrei();

12
src/cpu/ozone/dyn_inst_impl.hh
View File

@@ -223,24 +223,24 @@ OzoneDynInst<Impl>::readMiscReg(int misc_reg)
template <class Impl>
TheISA::MiscReg
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
{
return this->thread->readMiscRegWithEffect(misc_reg, fault);
return this->thread->readMiscRegWithEffect(misc_reg);
}
template <class Impl>
Fault
void
OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
this->setIntResult(val);
return this->thread->setMiscReg(misc_reg, val);
this->thread->setMiscReg(misc_reg, val);
}
template <class Impl>
Fault
void
OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return this->thread->setMiscRegWithEffect(misc_reg, val);
this->thread->setMiscRegWithEffect(misc_reg, val);
}
#if FULL_SYSTEM

4
src/cpu/ozone/simple_cpu_builder.cc
View File

@@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;

9
src/cpu/ozone/simple_params.hh
View File

@@ -34,8 +34,11 @@
#include "cpu/ozone/cpu.hh"
//Forward declarations
class AlphaDTB;
class AlphaITB;
namespace TheISA
{
class DTB;
class ITB;
}
class FUPool;
class MemObject;
class PageTable;
@@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params
public:
#if FULL_SYSTEM
AlphaITB *itb; AlphaDTB *dtb;
TheISA::ITB *itb; TheISA::DTB *dtb;
#else
std::vector<Process *> workload;
#endif // FULL_SYSTEM

10
src/cpu/ozone/thread_state.hh
View File

@@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState {
return miscRegFile.readReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
return miscRegFile.setReg(misc_reg, val);
miscRegFile.setReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return miscRegFile.setRegWithEffect(misc_reg, val, tc);
miscRegFile.setRegWithEffect(misc_reg, val, tc);
}
uint64_t readPC()

8
src/cpu/simple/base.hh
View File

@@ -288,17 +288,17 @@ class BaseSimpleCPU : public BaseCPU
return thread->readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return thread->readMiscRegWithEffect(misc_reg, fault);
return thread->readMiscRegWithEffect(misc_reg);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
return thread->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return thread->setMiscRegWithEffect(misc_reg, val);
}

8
src/cpu/simple_thread.hh
View File

@@ -420,17 +420,17 @@ class SimpleThread : public ThreadState
return regs.readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
MiscReg readMiscRegWithEffect(int misc_reg)
{
return regs.readMiscRegWithEffect(misc_reg, fault, tc);
return regs.readMiscRegWithEffect(misc_reg, tc);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
return regs.setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return regs.setMiscRegWithEffect(misc_reg, val, tc);
}

14
src/cpu/thread_context.hh
View File

@@ -224,11 +224,11 @@ class ThreadContext
virtual MiscReg readMiscReg(int misc_reg) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
@@ -410,13 +410,13 @@ class ProxyThreadContext : public ThreadContext
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{ return actualTC->readMiscRegWithEffect(misc_reg, fault); }
MiscReg readMiscRegWithEffect(int misc_reg)
{ return actualTC->readMiscRegWithEffect(misc_reg); }
Fault setMiscReg(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscReg(misc_reg, val); }
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscRegWithEffect(misc_reg, val); }
unsigned readStCondFailures()