misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).

src/dev/alpha/backdoor.hh

@@ -107,13 +107,13 @@ class AlphaBackdoor : public BasicPioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual void startup();
+    void startup() override;
 
     /**
      * memory mapped reads and writes
      */
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     /**
      * standard serialization routines for checkpointing

src/dev/alpha/tsunami.hh

@@ -80,7 +80,7 @@ class Tsunami : public Platform
     int intr_sum_type[Tsunami::Max_CPUs];
     int ipi_pending[Tsunami::Max_CPUs];
 
-    void init();
+    void init() override;
 
   public:
     typedef TsunamiParams Params;
@@ -89,40 +89,40 @@ class Tsunami : public Platform
     /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
-    virtual void postConsoleInt();
+    void postConsoleInt() override;
 
     /**
      * Clear a posted CPU interrupt (id=55)
      */
-    virtual void clearConsoleInt();
+    void clearConsoleInt() override;
 
     /**
      * Cause the chipset to post a cpi interrupt to the CPU.
      */
-    virtual void postPciInt(int line);
+    void postPciInt(int line) override;
 
     /**
      * Clear a posted PCI->CPU interrupt
      */
-    virtual void clearPciInt(int line);
+    void clearPciInt(int line) override;
 
 
-    virtual Addr pciToDma(Addr pciAddr) const;
+    Addr pciToDma(Addr pciAddr) const override;
 
     /**
      * Calculate the configuration address given a bus/dev/func.
      */
-    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+    Addr calcPciConfigAddr(int bus, int dev, int func) override;
 
     /**
      * Calculate the address for an IO location on the PCI bus.
      */
-    virtual Addr calcPciIOAddr(Addr addr);
+    Addr calcPciIOAddr(Addr addr) override;
 
     /**
      * Calculate the address for a memory location on the PCI bus.
      */
-    virtual Addr calcPciMemAddr(Addr addr);
+    Addr calcPciMemAddr(Addr addr) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/alpha/tsunami_cchip.hh

@@ -92,9 +92,9 @@ class TsunamiCChip : public BasicPioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual Tick read(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
 
-    virtual Tick write(PacketPtr pkt);
+    Tick write(PacketPtr pkt) override;
 
     /**
      * post an RTC interrupt to the CPU

src/dev/alpha/tsunami_io.hh

@@ -123,8 +123,8 @@ class TsunamiIO : public BasicPioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     /**
      * Post an PIC interrupt to the CPU via the CChip
@@ -144,7 +144,7 @@ class TsunamiIO : public BasicPioDevice
     /**
      * Start running.
      */
-    virtual void startup();
+    void startup() override;
 
 };
 

src/dev/alpha/tsunami_pchip.hh

@@ -86,8 +86,8 @@ class TsunamiPChip : public BasicPioDevice
     Addr calcIOAddr(Addr addr);
     Addr calcMemAddr(Addr addr);
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/copy_engine.hh

@@ -196,13 +196,13 @@ class CopyEngine : public PciDevice
     CopyEngine(const Params *params);
     ~CopyEngine();
 
-    void regStats();
+    void regStats() override;
 
-    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
-                                          PortID idx = InvalidPortID);
+    BaseMasterPort &getMasterPort(const std::string &if_name,
+                                  PortID idx = InvalidPortID) override;
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/disk_image.hh

@@ -132,10 +132,10 @@ class CowDiskImage : public DiskImage
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
 
-    virtual std::streampos size() const;
+    std::streampos size() const override;
 
-    virtual std::streampos read(uint8_t *data, std::streampos offset) const;
-    virtual std::streampos write(const uint8_t *data, std::streampos offset);
+    std::streampos read(uint8_t *data, std::streampos offset) const override;
+    std::streampos write(const uint8_t *data, std::streampos offset) override;
 };
 
 void SafeRead(std::ifstream &stream, void *data, int count);

src/dev/dma_device.hh

@@ -134,8 +134,8 @@ class DmaPort : public MasterPort, public Drainable
 
   protected:
 
-    bool recvTimingResp(PacketPtr pkt);
-    void recvReqRetry() ;
+    bool recvTimingResp(PacketPtr pkt) override;
+    void recvReqRetry() override;
 
     void queueDma(PacketPtr pkt);
 
@@ -175,12 +175,12 @@ class DmaDevice : public PioDevice
 
     bool dmaPending() const { return dmaPort.dmaPending(); }
 
-    virtual void init();
+    void init() override;
 
     unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
 
-    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
-                                          PortID idx = InvalidPortID);
+    BaseMasterPort &getMasterPort(const std::string &if_name,
+                                  PortID idx = InvalidPortID) override;
 
 };
 

src/dev/etherlink.hh

@@ -156,7 +156,7 @@ class EtherLink : public EtherObject
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+    EtherInt *getEthPort(const std::string &if_name, int idx) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/ethertap.hh

@@ -110,7 +110,7 @@ class EtherTap : public EtherObject
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+    EtherInt *getEthPort(const std::string &if_name, int idx) override;
 
     virtual bool recvPacket(EthPacketPtr packet);
     virtual void sendDone();

src/dev/i2cbus.hh

@@ -143,8 +143,8 @@ class I2CBus : public BasicPioDevice
 
     I2CBus(const I2CBusParams* p);
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/i8254xGBe.hh

@@ -342,13 +342,13 @@ class IGbE : public EtherDevice
     class RxDescCache : public DescCache<iGbReg::RxDesc>
     {
       protected:
-        virtual Addr descBase() const { return igbe->regs.rdba(); }
-        virtual long descHead() const { return igbe->regs.rdh(); }
-        virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
-        virtual long descTail() const { return igbe->regs.rdt(); }
-        virtual void updateHead(long h) { igbe->regs.rdh(h); }
-        virtual void enableSm();
-        virtual void fetchAfterWb() {
+        Addr descBase() const override { return igbe->regs.rdba(); }
+        long descHead() const override { return igbe->regs.rdh(); }
+        long descLen() const override { return igbe->regs.rdlen() >> 4; }
+        long descTail() const override { return igbe->regs.rdt(); }
+        void updateHead(long h) override { igbe->regs.rdh(h); }
+        void enableSm() override;
+        void fetchAfterWb() override {
             if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
                 fetchDescriptors();
         }
@@ -391,7 +391,7 @@ class IGbE : public EtherDevice
         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
 
-        virtual bool hasOutstandingEvents();
+        bool hasOutstandingEvents() override;
 
         void serialize(CheckpointOut &cp) const override;
         void unserialize(CheckpointIn &cp) override;
@@ -403,14 +403,14 @@ class IGbE : public EtherDevice
     class TxDescCache  : public DescCache<iGbReg::TxDesc>
     {
       protected:
-        virtual Addr descBase() const { return igbe->regs.tdba(); }
-        virtual long descHead() const { return igbe->regs.tdh(); }
-        virtual long descTail() const { return igbe->regs.tdt(); }
-        virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
-        virtual void updateHead(long h) { igbe->regs.tdh(h); }
-        virtual void enableSm();
-        virtual void actionAfterWb();
-        virtual void fetchAfterWb() {
+        Addr descBase() const override { return igbe->regs.tdba(); }
+        long descHead() const override { return igbe->regs.tdh(); }
+        long descTail() const override { return igbe->regs.tdt(); }
+        long descLen() const override { return igbe->regs.tdlen() >> 4; }
+        void updateHead(long h) override { igbe->regs.tdh(h); }
+        void enableSm() override;
+        void actionAfterWb() override;
+        void fetchAfterWb() override {
             if (!igbe->txTick && igbe->drainState() == DrainState::Running)
                 fetchDescriptors();
         }
@@ -497,7 +497,7 @@ class IGbE : public EtherDevice
             completionEnabled = enabled;
         }
 
-        virtual bool hasOutstandingEvents();
+        bool hasOutstandingEvents() override;
 
         void nullCallback() {
             DPRINTF(EthernetDesc, "Completion writeback complete\n");
@@ -521,16 +521,16 @@ class IGbE : public EtherDevice
 
     IGbE(const Params *params);
     ~IGbE();
-    virtual void init();
+    void init() override;
 
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+    EtherInt *getEthPort(const std::string &if_name, int idx) override;
 
     Tick lastInterrupt;
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
-    virtual Tick writeConfig(PacketPtr pkt);
+    Tick writeConfig(PacketPtr pkt) override;
 
     bool ethRxPkt(EthPacketPtr packet);
     void ethTxDone();

src/dev/ide_ctrl.hh

@@ -146,13 +146,13 @@ class IdeController : public PciDevice
 
     void intrPost();
 
-    Tick writeConfig(PacketPtr pkt);
-    Tick readConfig(PacketPtr pkt);
+    Tick writeConfig(PacketPtr pkt) override;
+    Tick readConfig(PacketPtr pkt) override;
 
     void setDmaComplete(IdeDisk *disk);
 
-    Tick read(PacketPtr pkt);
-    Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

src/dev/ide_disk.hh

@@ -276,7 +276,7 @@ class IdeDisk : public SimObject
     /**
      * Register Statistics
      */
-    void regStats();
+    void regStats() override;
 
     /**
      * Set the controller for this device

src/dev/ns_gige.hh

@@ -353,12 +353,12 @@ class NSGigE : public EtherDevBase
     NSGigE(Params *params);
     ~NSGigE();
 
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+    EtherInt *getEthPort(const std::string &if_name, int idx) override;
 
-    virtual Tick writeConfig(PacketPtr pkt);
+    Tick writeConfig(PacketPtr pkt) override;
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     bool cpuIntrPending() const;
     void cpuIntrAck() { cpuIntrClear(); }

src/dev/pcidev.hh

@@ -76,9 +76,9 @@ class PciDevice : public DmaDevice
       protected:
         PciDevice *device;
 
-        virtual Tick recvAtomic(PacketPtr pkt);
+        Tick recvAtomic(PacketPtr pkt) override;
 
-        virtual AddrRangeList getAddrRanges() const;
+        AddrRangeList getAddrRanges() const override;
 
         Platform *platform;
 
@@ -234,7 +234,7 @@ class PciDevice : public DmaDevice
      *
      * @return a list of non-overlapping address ranges
      */
-    AddrRangeList getAddrRanges() const;
+    AddrRangeList getAddrRanges() const override;
 
     /**
      * Constructor for PCI Dev. This function copies data from the
@@ -243,7 +243,7 @@ class PciDevice : public DmaDevice
      */
     PciDevice(const Params *params);
 
-    virtual void init();
+    void init() override;
 
     /**
      * Serialize this object to the given output stream.
@@ -259,8 +259,8 @@ class PciDevice : public DmaDevice
     void unserialize(CheckpointIn &cp) override;
 
 
-    virtual BaseSlavePort &getSlavePort(const std::string &if_name,
-                                        PortID idx = InvalidPortID)
+    BaseSlavePort &getSlavePort(const std::string &if_name,
+                                PortID idx = InvalidPortID) override
     {
         if (if_name == "config") {
             return configPort;

src/dev/sinic.hh

@@ -238,7 +238,7 @@ class Device : public Base
   public:
     bool recvPacket(EthPacketPtr packet);
     void transferDone();
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+    EtherInt *getEthPort(const std::string &if_name, int idx) override;
 
 /**
  * DMA parameters
@@ -269,8 +269,8 @@ class Device : public Base
  * Memory Interface
  */
   public:
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
     virtual void drainResume() override;
 
     void prepareIO(ContextID cpu, int index);
@@ -290,8 +290,8 @@ class Device : public Base
     int _maxVnicDistance;
 
   public:
-    virtual void regStats();
-    virtual void resetStats();
+    void regStats() override;
+    void resetStats() override;
 
 /**
  * Serialization stuff

src/dev/uart8250.hh

@@ -97,14 +97,14 @@ class Uart8250 : public Uart
     }
     Uart8250(const Params *p);
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
-    virtual AddrRangeList getAddrRanges() const;
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
+    AddrRangeList getAddrRanges() const override;
 
     /**
      * Inform the uart that there is data available.
      */
-    virtual void dataAvailable();
+    void dataAvailable() override;
 
 
     /**

src/dev/virtio/fs9p.hh

@@ -220,7 +220,8 @@ class VirtIO9PProxy : public VirtIO9PBase
     void unserialize(CheckpointIn &cp) override;
 
   protected:
-    void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size);
+    void recvTMsg(const P9MsgHeader &header, const uint8_t *data,
+                  size_t size) override;
 
     /** Notification of pending data from server */
     void serverDataReady();