diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 729b60aa35..fbf877336f 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -283,30 +283,18 @@ class RegOperandDesc(OperandDesc):
         super().__init__(*args, **kwargs)
         self.attrs['reg_class'] = reg_class
 
-class IntRegOperand(RegValOperand):
-    reg_class = 'IntRegClass'
-
 class IntRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
         super().__init__('IntRegClass', RegValOperand, *args, **kwargs)
 
-class FloatRegOperand(RegValOperand):
-    reg_class = 'FloatRegClass'
-
 class FloatRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
         super().__init__('FloatRegClass', RegValOperand, *args, **kwargs)
 
-class CCRegOperand(RegValOperand):
-    reg_class = 'CCRegClass'
-
 class CCRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
         super().__init__('CCRegClass', RegValOperand, *args, **kwargs)
 
-class VecElemOperand(RegValOperand):
-    reg_class = 'VecElemClass'
-
 class VecElemOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
         super().__init__('VecElemClass', RegValOperand, *args, **kwargs)