From f7a75d872b4bf94aafcfcb5f773afda75f7c3499 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 3 Feb 2006 03:38:27 -0500 Subject: [PATCH 1/7] Checkin (Merge?) files ... Added a few new format files arch/mips/isa/formats/fpop.format: Floating Point Formats arch/mips/isa/formats/tlb.format: TLB Ops Format arch/mips/isa/mips.isa: Name change to mips.isa --HG-- rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed --- arch/mips/{isa_desc => isa}/bitfields.h | 0 arch/mips/{isa_desc => isa}/decoder.h | 0 arch/mips/{isa_desc => isa}/formats.h | 0 .../{isa_desc => isa}/formats/basic.format | 0 .../{isa_desc => isa}/formats/branch.format | 0 arch/mips/isa/formats/fpop.format | 110 ++++++++++++++++++ .../formats/integerop.format | 0 .../mips/{isa_desc => isa}/formats/mem.format | 0 .../{isa_desc => isa}/formats/noop.format | 0 arch/mips/isa/formats/tlb.format | 53 +++++++++ .../{isa_desc => isa}/formats/trap.format | 0 arch/mips/{isa_desc => isa}/includes.h | 0 arch/mips/isa/mips.isa | 52 +++++++++ arch/mips/{isa_desc => isa}/operands.h | 0 14 files changed, 215 insertions(+) rename arch/mips/{isa_desc => isa}/bitfields.h (100%) rename arch/mips/{isa_desc => isa}/decoder.h (100%) rename arch/mips/{isa_desc => isa}/formats.h (100%) rename arch/mips/{isa_desc => isa}/formats/basic.format (100%) rename arch/mips/{isa_desc => isa}/formats/branch.format (100%) create mode 100644 arch/mips/isa/formats/fpop.format rename arch/mips/{isa_desc => isa}/formats/integerop.format (100%) rename arch/mips/{isa_desc => isa}/formats/mem.format (100%) rename arch/mips/{isa_desc => isa}/formats/noop.format (100%) create mode 100644 arch/mips/isa/formats/tlb.format rename arch/mips/{isa_desc => isa}/formats/trap.format (100%) rename arch/mips/{isa_desc => isa}/includes.h (100%) create mode 100644 arch/mips/isa/mips.isa rename arch/mips/{isa_desc => isa}/operands.h (100%) diff --git a/arch/mips/isa_desc/bitfields.h b/arch/mips/isa/bitfields.h similarity index 100% rename from arch/mips/isa_desc/bitfields.h rename to arch/mips/isa/bitfields.h diff --git a/arch/mips/isa_desc/decoder.h b/arch/mips/isa/decoder.h similarity index 100% rename from arch/mips/isa_desc/decoder.h rename to arch/mips/isa/decoder.h diff --git a/arch/mips/isa_desc/formats.h b/arch/mips/isa/formats.h similarity index 100% rename from arch/mips/isa_desc/formats.h rename to arch/mips/isa/formats.h diff --git a/arch/mips/isa_desc/formats/basic.format b/arch/mips/isa/formats/basic.format similarity index 100% rename from arch/mips/isa_desc/formats/basic.format rename to arch/mips/isa/formats/basic.format diff --git a/arch/mips/isa_desc/formats/branch.format b/arch/mips/isa/formats/branch.format similarity index 100% rename from arch/mips/isa_desc/formats/branch.format rename to arch/mips/isa/formats/branch.format diff --git a/arch/mips/isa/formats/fpop.format b/arch/mips/isa/formats/fpop.format new file mode 100644 index 0000000000..a058eea19f --- /dev/null +++ b/arch/mips/isa/formats/fpop.format @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Floating Point operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class FPOp : public MipsStaticInst + { + protected: + + /// Constructor + FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template IntegerExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format FPOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/integerop.format b/arch/mips/isa/formats/integerop.format similarity index 100% rename from arch/mips/isa_desc/formats/integerop.format rename to arch/mips/isa/formats/integerop.format diff --git a/arch/mips/isa_desc/formats/mem.format b/arch/mips/isa/formats/mem.format similarity index 100% rename from arch/mips/isa_desc/formats/mem.format rename to arch/mips/isa/formats/mem.format diff --git a/arch/mips/isa_desc/formats/noop.format b/arch/mips/isa/formats/noop.format similarity index 100% rename from arch/mips/isa_desc/formats/noop.format rename to arch/mips/isa/formats/noop.format diff --git a/arch/mips/isa/formats/tlb.format b/arch/mips/isa/formats/tlb.format new file mode 100644 index 0000000000..f5e4076f29 --- /dev/null +++ b/arch/mips/isa/formats/tlb.format @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// TlbOp instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class TlbOp : public MipsStaticInst + { + protected: + + /// Constructor + TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TlbOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format TlbOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TlbOpExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/trap.format b/arch/mips/isa/formats/trap.format similarity index 100% rename from arch/mips/isa_desc/formats/trap.format rename to arch/mips/isa/formats/trap.format diff --git a/arch/mips/isa_desc/includes.h b/arch/mips/isa/includes.h similarity index 100% rename from arch/mips/isa_desc/includes.h rename to arch/mips/isa/includes.h diff --git a/arch/mips/isa/mips.isa b/arch/mips/isa/mips.isa new file mode 100644 index 0000000000..a8c71872be --- /dev/null +++ b/arch/mips/isa/mips.isa @@ -0,0 +1,52 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2003-2005 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +##include "m5/arch/sparc/isa_desc/includes.h" + +//////////////////////////////////////////////////////////////////// +// +// Namespace statement. Everything below this line will be in the +// MipsISAInst namespace. +// + +namespace MipsISA; + +//Include the bitfield definitions +##include "m5/arch/mips/isa_desc/bitfields.h" + +//Include the operand_types and operand definitions +##include "m5/arch/mips/isa_desc/operands.h" + +//Include the base class for mips instructions, and some support code +##include "m5/arch/mips/isa_desc/base.h" + +//Include the definitions for the instruction formats +##include "m5/arch/mips/isa_desc/formats.h" + +//Include the decoder definition +##include "m5/arch/mips/isa_desc/decoder.h" diff --git a/arch/mips/isa_desc/operands.h b/arch/mips/isa/operands.h similarity index 100% rename from arch/mips/isa_desc/operands.h rename to arch/mips/isa/operands.h From de1f3a7b6bd21845faaf48c8fa509a432c01c165 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 3 Feb 2006 03:39:08 -0500 Subject: [PATCH 2/7] Rename: arch/mips/isa/formats/tlb.format -> arch/mips/isa/formats/tlbop.format --HG-- rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format extra : convert_revision : 5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde --- arch/mips/isa/formats/{tlb.format => tlbop.format} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/mips/isa/formats/{tlb.format => tlbop.format} (100%) diff --git a/arch/mips/isa/formats/tlb.format b/arch/mips/isa/formats/tlbop.format similarity index 100% rename from arch/mips/isa/formats/tlb.format rename to arch/mips/isa/formats/tlbop.format From 1e222c1502f8cf40535fed23b3f51c5f25a6c29f Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 3 Feb 2006 03:56:57 -0500 Subject: [PATCH 3/7] .h -> .def --HG-- rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def extra : convert_revision : 45cb5485311d51982ebcaf1c7eec34e8751c31f5 --- arch/mips/isa/{bitfields.h => bitfields.def} | 8 +- arch/mips/isa/decoder.def | 575 +++++++++++++++++++ arch/mips/isa/decoder.h | 575 ------------------- arch/mips/isa/{formats.h => formats.def} | 0 arch/mips/isa/{operands.h => operands.def} | 0 5 files changed, 579 insertions(+), 579 deletions(-) rename arch/mips/isa/{bitfields.h => bitfields.def} (88%) create mode 100644 arch/mips/isa/decoder.def delete mode 100644 arch/mips/isa/decoder.h rename arch/mips/isa/{formats.h => formats.def} (100%) rename arch/mips/isa/{operands.h => operands.def} (100%) diff --git a/arch/mips/isa/bitfields.h b/arch/mips/isa/bitfields.def similarity index 88% rename from arch/mips/isa/bitfields.h rename to arch/mips/isa/bitfields.def index f0d6fc8d75..0a94978996 100644 --- a/arch/mips/isa/bitfields.h +++ b/arch/mips/isa/bitfields.def @@ -41,11 +41,11 @@ def bitfield INTIMM <15: 0>; // integer immediate (literal) def bitfield OFFSET <15: 0>; // displacement // Memory-format jumps -def bitfield JMPTARG <25: 0>; -def bitfield JMPHINT <10: 6>; +def bitfield JMPTARG <25: 0>; +def bitfield JMPHINT <10: 6>; -def bitfield SYSCALLCODE <25: 6>; -def bitfield TRAPCODE <15:13>; +def bitfield SYSCALLCODE <25: 6>; +def bitfield TRAPCODE <15:13>; // M5 instructions def bitfield M5FUNC <7:0>; diff --git a/arch/mips/isa/decoder.def b/arch/mips/isa/decoder.def new file mode 100644 index 0000000000..49066c9bf8 --- /dev/null +++ b/arch/mips/isa/decoder.def @@ -0,0 +1,575 @@ +//////////////////////////////////////////////////////////////////// +// +// The actual MIPS32 ISA decoder +// ----------------------------- +// The following instructions are specified in the MIPS32 ISA +// Specification. Decoding closely follows the style specified +// in the MIPS32 ISAthe specification document starting with Table +// A-2 (document available @ www.mips.com) +// +//@todo: Distinguish "unknown/future" use insts from "reserved" +// ones +decode OPCODE_HI default FailUnimpl::unknown() { + + // Derived From ... Table A-2 MIPS32 ISA Manual + 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ + + 0x0: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x1: decode MOVCI { + format Move { + 0: movc({{ }}); + 1: movt({{ }}); + } + } + + format ShiftRotate { + //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields + //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." + 0x0: sll({{ }}); + + 0x2: decode SRL { + 0: srl({{ }}); + 1: rotr({{ }}); + } + + 0x3: sar({{ }}); + + 0x4: sllv({{ }}); + + 0x6: decode SRLV { + 0: srlv({{ }}); + 1: rotrv({{ }}); + } + + 0x7: srav({{ }}); + } + } + + 0x1: decode FUNCTION_LO { + + //Table A-3 Note: "Specific encodings of the hint field are used + //to distinguish JR from JR.HB and JALR from JALR.HB" + format Jump { + 0x0: jr({{ }}); + 0x1: jalr({{ }}); + } + + format Move { + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: Syscall::syscall({{ }}); + 0x5: Break::break({{ }}); + 0x7: Synchronize::synch({{ }}); + } + + 0x2: decode FUNCTION_LO { + format MultDiv { + 0x0: mfhi({{ }}); + 0x1: mthi({{ }}); + 0x2: mflo({{ }}); + 0x3: mtlo({{ }}); + } + }; + + 0x3: decode FUNCTION_LO { + format MultDiv { + 0x0: mult({{ }}); + 0x1: multu({{ }}); + 0x2: div({{ }}); + 0x3: divu({{ }}); + } + }; + + 0x4: decode FUNCTION_LO { + format Arithmetic { + 0x0: add({{ }}); + 0x1: addu({{ }}); + 0x2: sub({{ }}); + 0x3: subu({{ }}); + } + + format Logical { + 0x0: and({{ }}); + 0x1: or({{ }}); + 0x2: xor({{ }}); + 0x3: nor({{ }}); + } + } + + 0x5: decode FUNCTION_LO { + format SetInstructions{ + 0x2: slt({{ }}); + 0x3: sltu({{ }}); + } + }; + + 0x6: decode FUNCTION_LO { + format Trap { + 0x0: tge({{ }}); + 0x1: tgeu({{ }}); + 0x2: tlt({{ }}); + 0x3: tltu({{ }}); + 0x4: teq({{ }}); + 0x6: tne({{ }}); + } + } + } + + 0x1: decode REGIMM_HI { + 0x0: decode REGIMM_LO { + format Branch { + 0x0: bltz({{ }}); + 0x1: bgez({{ }}); + + //MIPS obsolete instructions + 0x2: bltzl({{ }}); + 0x3: bgezl({{ }}); + } + } + + 0x1: decode REGIMM_LO { + format Trap { + 0x0: tgei({{ }}); + 0x1: tgeiu({{ }}); + 0x2: tlti({{ }}); + 0x3: tltiu({{ }}); + 0x4: teqi({{ }}); + 0x6: tnei({{ }}); + } + } + + 0x2: decode REGIMM_LO { + format Branch { + 0x0: bltzal({{ }}); + 0x1: bgezal({{ }}); + + //MIPS obsolete instructions + 0x2: bltzall({{ }}); + 0x3: bgezall({{ }}); + } + } + + 0x3: decode REGIMM_LO { + 0x7: synci({{ }}); + } + } + + format Jump { + 0x2: j({{ }}); + 0x3: jal({{ }}); + } + + format Branch { + 0x4: beq({{ }}); + 0x5: bne({{ }}); + 0x6: blez({{ }}); + 0x7: bgtz({{ }}); + } + }; + + 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ + format IntImmediate { + 0x0: addi({{ }}); + 0x1: addiu({{ }}); + 0x2: slti({{ }}); + 0x3: sltiu({{ }}); + 0x4: andi({{ }}); + 0x5: ori({{ }}); + 0x6: xori({{ }}); + 0x7: lui({{ }}); + }; + }; + + 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-11 MIPS32 COP0 Encoding of rs Field + 0x0: decode RS_MSB { + 0x0: decode RS { + 0x0: mfc0({{ }}); + 0xC: mtc0({{ }}); + 0xA: rdpgpr({{ }}); + + 0xB: decode SC { + 0x0: di({{ }}); + 0x1: ei({{ }}); + } + + 0xE: wrpgpr({{ }}); + } + + //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO + 0x1: decode FUNCTION { + 0x01: tlbr({{ }}); + 0x02: tlbwi({{ }}); + 0x06: tlbwr({{ }}); + 0x08: tlbp({{ }}); + 0x18: eret({{ }}); + 0x1F: deret({{ }}); + 0x20: wait({{ }}); + } + } + + //Table A-13 MIPS32 COP1 Encoding of rs Field + 0x1: decode RS_MSB { + + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc1({{ }}); + 0x2: cfc1({{ }}); + 0x3: mfhc1({{ }}); + 0x4: mtc1({{ }}); + 0x6: ctc1({{ }}); + 0x7: mftc1({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc1f({{ }}); + 0x1: bc1t({{ }}); + } + + 0x1: decode TF { + 0x0: bc1fl({{ }}); + 0x1: bc1tl({{ }}); + } + } + } + + 0x1: decode RS_HI { + 0x2: decode RS_LO { + + //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S + //(( single-word )) + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x2: recip({{ }}); + 0x3: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x1: cvt_d({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + 0x6: cvt_ps({{ }}); + } + } + } + + //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D + 0x1: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x5: recip({{ }}); + 0x6: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x0: cvt_s({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + } + } + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W + 0x4: decode FUNCTION { + 0x10: cvt_s({{ }}); + 0x10: cvt_d({{ }}); + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 + //Note: "1. Format type L is legal only if 64-bit floating point operations + //are enabled." + 0x5: decode FUNCTION_HI { + 0x10: cvt_s({{ }}); + 0x11: cvt_d({{ }}); + } + + //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 + //Note: "1. Format type PS is legal only if 64-bit floating point operations + //are enabled. " + 0x6: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: decode RS_LO { + 0x0: cvt_s_pu({{ }}); + } + + 0x5: decode RS_LO { + 0x0: cvt_s_pl({{ }}); + 0x4: pll_s_pl({{ }}); + 0x5: plu_s_pl({{ }}); + 0x6: pul_s_pl({{ }}); + 0x7: puu_s_pl({{ }}); + } + } + } + + //Table A-19 MIPS32 COP2 Encoding of rs Field + 0x2: decode RS_MSB { + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc2({{ }}); + 0x2: cfc2({{ }}); + 0x3: mfhc2({{ }}); + 0x4: mtc2({{ }}); + 0x6: ctc2({{ }}); + 0x7: mftc2({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc2f({{ }}); + 0x1: bc2t({{ }}); + } + + 0x1: decode TF { + 0x0: bc2fl({{ }}); + 0x1: bc2tl({{ }}); + } + } + } + } + + //Table A-20 MIPS64 COP1X Encoding of Function Field 1 + //Note: "COP1X instructions are legal only if 64-bit floating point + //operations are enabled." + 0x3: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x0: lwxc1({{ }}); + 0x1: ldxc1({{ }}); + 0x5: luxc1({{ }}); + } + + 0x1: decode FUNCTION_LO { + 0x0: swxc1({{ }}); + 0x1: sdxc1({{ }}); + 0x5: suxc1({{ }}); + 0x7: prefx({{ }}); + } + + 0x3: alnv_ps({{ }}); + + 0x4: decode FUNCTION_LO { + 0x0: madd_s({{ }}); + 0x1: madd_d({{ }}); + 0x6: madd_ps({{ }}); + } + + 0x5: decode FUNCTION_LO { + 0x0: msub_s({{ }}); + 0x1: msub_d({{ }}); + 0x6: msub_ps({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x0: nmadd_s({{ }}); + 0x1: nmadd_d({{ }}); + 0x6: nmadd_ps({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x0: nmsub_s({{ }}); + 0x1: nmsub_d({{ }}); + 0x6: nmsub_ps({{ }}); + } + } + + //MIPS obsolete instructions + 0x4: beql({{ }}); + 0x5: bnel({{ }}); + 0x6: blezl({{ }}); + 0x7: bgtzl({{ }}); + }; + + 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field + 0x4: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x0: madd({{ }}); + 0x1: maddu({{ }}); + 0x2: mult({{ }}); + 0x4: msub({{ }}); + 0x5: msubu({{ }}); + } + + 0x4: decode FUNCTION_LO { + 0x0: clz({{ }}); + 0x1: clo({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x7: sdbbp({{ }}); + } + } + + //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture + 0x7: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x1: ext({{ }}); + 0x4: ins({{ }}); + } + + //Table A-10 MIPS32 BSHFL Encoding of sa Field + 0x4: decode SA { + 0x02: wsbh({{ }}); + 0x10: seb({{ }}); + 0x18: seh({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x7: rdhwr({{ }}); + } + } + }; + + 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: lb({{ }}); + 0x1: lh({{ }}); + 0x2: lwl({{ }}); + 0x3: lw({{ }}); + 0x4: lbu({{ }}); + 0x5: lhu({{ }}); + 0x6: lhu({{ }}); + }; + + 0x7: FailUnimpl::reserved({{ }}); + }; + + 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sb({{ }}); + 0x1: sh({{ }}); + 0x2: swl({{ }}); + 0x3: sw({{ }}); + 0x6: swr({{ }}); + }; + + format FailUnimpl{ + 0x4: reserved({{ }}); + 0x5: reserved({{ }}); + 0x7: cache({{ }}); + }; + + }; + + 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: ll({{ }}); + 0x1: lwc1({{ }}); + 0x5: ldc1({{ }}); + }; + }; + + 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sc({{ }}); + 0x1: swc1({{ }}); + 0x5: sdc1({{ }}); + }; + + } +} + + diff --git a/arch/mips/isa/decoder.h b/arch/mips/isa/decoder.h deleted file mode 100644 index 7e911cb452..0000000000 --- a/arch/mips/isa/decoder.h +++ /dev/null @@ -1,575 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// The actual MIPS32 ISA decoder -// ----------------------------- -// The following instructions are specified in the MIPS32 ISA -// Specification. Decoding closely follows the style specified -// in the MIPS32 ISAthe specification document starting with Table -// A-2 (document available @ www.mips.com) -// -//@todo: Distinguish "unknown/future" use insts from "reserved" -// ones -decode OPCODE_HI default FailUnimpl::unknown() { - - // Derived From ... Table A-2 MIPS32 ISA Manual - 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ - - 0x0: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x1: decode MOVCI { - format Move { - 0: movc({{ }}); - 1: movt({{ }}); - } - } - - format ShiftRotate { - //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields - //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - 0x0: sll({{ }}); - - 0x2: decode SRL { - 0: srl({{ }}); - 1: rotr({{ }}); - } - - 0x3: sar({{ }}); - - 0x4: sllv({{ }}); - - 0x6: decode SRLV { - 0: srlv({{ }}); - 1: rotrv({{ }}); - } - - 0x7: srav({{ }}); - } - } - - 0x1: decode FUNCTION_LO { - - //Table A-3 Note: "Specific encodings of the hint field are used - //to distinguish JR from JR.HB and JALR from JALR.HB" - format Jump { - 0x0: jr({{ }}); - 0x1: jalr({{ }}); - } - - format Move { - 0x2: movz({{ }}); - 0x3: movn({{ }}); - } - - 0x4: Syscall::syscall({{ }}); - 0x5: Break::break({{ }}); - 0x7: Synchronize::synch({{ }}); - } - - 0x2: decode FUNCTION_LO { - format MultDiv { - 0x0: mfhi({{ }}); - 0x1: mthi({{ }}); - 0x2: mflo({{ }}); - 0x3: mtlo({{ }}); - } - }; - - 0x3: decode FUNCTION_LO { - format MultDiv { - 0x0: mult({{ }}); - 0x1: multu({{ }}); - 0x2: div({{ }}); - 0x3: divu({{ }}); - } - }; - - 0x4: decode FUNCTION_LO { - format Arithmetic { - 0x0: add({{ }}); - 0x1: addu({{ }}); - 0x2: sub({{ }}); - 0x3: subu({{ }}); - } - - format Logical { - 0x0: and({{ }}); - 0x1: or({{ }}); - 0x2: xor({{ }}); - 0x3: nor({{ }}); - } - } - - 0x5: decode FUNCTION_LO { - format SetInstructions{ - 0x2: slt({{ }}); - 0x3: sltu({{ }}); - } - }; - - 0x6: decode FUNCTION_LO { - format Trap { - 0x0: tge({{ }}); - 0x1: tgeu({{ }}); - 0x2: tlt({{ }}); - 0x3: tltu({{ }}); - 0x4: teq({{ }}); - 0x6: tne({{ }}); - } - } - } - - 0x1: decode REGIMM_HI { - 0x0: decode REGIMM_LO { - format Branch { - 0x0: bltz({{ }}); - 0x1: bgez({{ }}); - - //MIPS obsolete instructions - 0x2: bltzl({{ }}); - 0x3: bgezl({{ }}); - } - } - - 0x1: decode REGIMM_LO { - format Trap { - 0x0: tgei({{ }}); - 0x1: tgeiu({{ }}); - 0x2: tlti({{ }}); - 0x3: tltiu({{ }}); - 0x4: teqi({{ }}); - 0x6: tnei({{ }}); - } - } - - 0x2: decode REGIMM_LO { - format Branch { - 0x0: bltzal({{ }}); - 0x1: bgezal({{ }}); - - //MIPS obsolete instructions - 0x2: bltzall({{ }}); - 0x3: bgezall({{ }}); - } - } - - 0x3: decode REGIMM_LO { - 0x7: synci({{ }}); - } - } - - format Jump { - 0x2: j({{ }}); - 0x3: jal({{ }}); - } - - format Branch { - 0x4: beq({{ }}); - 0x5: bne({{ }}); - 0x6: blez({{ }}); - 0x7: bgtz({{ }}); - } - }; - - 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ - format IntImmediate { - 0x0: addi({{ }}); - 0x1: addiu({{ }}); - 0x2: slti({{ }}); - 0x3: sltiu({{ }}); - 0x4: andi({{ }}); - 0x5: ori({{ }}); - 0x6: xori({{ }}); - 0x7: lui({{ }}); - }; - }; - - 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ - - //Table A-11 MIPS32 COP0 Encoding of rs Field - 0x0: decode RS_MSB { - 0x0: decode RS { - 0x0: mfc0({{ }}); - 0xC: mtc0({{ }}); - 0xA: rdpgpr({{ }}); - - 0xB: decode SC { - 0x0: di({{ }}); - 0x1: ei({{ }}); - } - - 0xE: wrpgpr({{ }}); - } - - //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO - 0x1: decode FUNCTION { - 0x01: tlbr({{ }}); - 0x02: tlbwi({{ }}); - 0x06: tlbwr({{ }}); - 0x08: tlbp({{ }}); - 0x18: eret({{ }}); - 0x1F: deret({{ }}); - 0x20: wait({{ }}); - } - } - - //Table A-13 MIPS32 COP1 Encoding of rs Field - 0x1: decode RS_MSB { - - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc1({{ }}); - 0x2: cfc1({{ }}); - 0x3: mfhc1({{ }}); - 0x4: mtc1({{ }}); - 0x6: ctc1({{ }}); - 0x7: mftc1({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - 0x0: bc1f({{ }}); - 0x1: bc1t({{ }}); - } - - 0x1: decode TF { - 0x0: bc1fl({{ }}); - 0x1: bc1tl({{ }}); - } - } - } - - 0x1: decode RS_HI { - 0x2: decode RS_LO { - - //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S - //(( single-word )) - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - - format mode64 { - 0x2: recip({{ }}); - 0x3: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x1: cvt_d({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - 0x6: cvt_ps({{ }}); - } - } - } - - //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D - 0x1: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - - format mode64 { - 0x5: recip({{ }}); - 0x6: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x0: cvt_s({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - } - } - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W - 0x4: decode FUNCTION { - 0x10: cvt_s({{ }}); - 0x10: cvt_d({{ }}); - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 - //Note: "1. Format type L is legal only if 64-bit floating point operations - //are enabled." - 0x5: decode FUNCTION_HI { - 0x10: cvt_s({{ }}); - 0x11: cvt_d({{ }}); - } - - //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 - //Note: "1. Format type PS is legal only if 64-bit floating point operations - //are enabled. " - 0x6: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - 0x2: movz({{ }}); - 0x3: movn({{ }}); - } - - 0x4: decode RS_LO { - 0x0: cvt_s_pu({{ }}); - } - - 0x5: decode RS_LO { - 0x0: cvt_s_pl({{ }}); - 0x4: pll_s_pl({{ }}); - 0x5: plu_s_pl({{ }}); - 0x6: pul_s_pl({{ }}); - 0x7: puu_s_pl({{ }}); - } - } - } - - //Table A-19 MIPS32 COP2 Encoding of rs Field - 0x2: decode RS_MSB { - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc2({{ }}); - 0x2: cfc2({{ }}); - 0x3: mfhc2({{ }}); - 0x4: mtc2({{ }}); - 0x6: ctc2({{ }}); - 0x7: mftc2({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - 0x0: bc2f({{ }}); - 0x1: bc2t({{ }}); - } - - 0x1: decode TF { - 0x0: bc2fl({{ }}); - 0x1: bc2tl({{ }}); - } - } - } - } - - //Table A-20 MIPS64 COP1X Encoding of Function Field 1 - //Note: "COP1X instructions are legal only if 64-bit floating point - //operations are enabled." - 0x3: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x0: lwxc1({{ }}); - 0x1: ldxc1({{ }}); - 0x5: luxc1({{ }}); - } - - 0x1: decode FUNCTION_LO { - 0x0: swxc1({{ }}); - 0x1: sdxc1({{ }}); - 0x5: suxc1({{ }}); - 0x7: prefx({{ }}); - } - - 0x3: alnv_ps({{ }}); - - 0x4: decode FUNCTION_LO { - 0x0: madd_s({{ }}); - 0x1: madd_d({{ }}); - 0x6: madd_ps({{ }}); - } - - 0x5: decode FUNCTION_LO { - 0x0: msub_s({{ }}); - 0x1: msub_d({{ }}); - 0x6: msub_ps({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x0: nmadd_s({{ }}); - 0x1: nmadd_d({{ }}); - 0x6: nmadd_ps({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x0: nmsub_s({{ }}); - 0x1: nmsub_d({{ }}); - 0x6: nmsub_ps({{ }}); - } - } - - //MIPS obsolete instructions - 0x4: beql({{ }}); - 0x5: bnel({{ }}); - 0x6: blezl({{ }}); - 0x7: bgtzl({{ }}); - }; - - 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ - - //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field - 0x4: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - 0x0: madd({{ }}); - 0x1: maddu({{ }}); - 0x2: mult({{ }}); - 0x4: msub({{ }}); - 0x5: msubu({{ }}); - } - - 0x4: decode FUNCTION_LO { - 0x0: clz({{ }}); - 0x1: clo({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x7: sdbbp({{ }}); - } - } - - //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture - 0x7: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - 0x1: ext({{ }}); - 0x4: ins({{ }}); - } - - //Table A-10 MIPS32 BSHFL Encoding of sa Field - 0x4: decode SA { - 0x02: wsbh({{ }}); - 0x10: seb({{ }}); - 0x18: seh({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x7: rdhwr({{ }}); - } - } - }; - - 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ - 0x0: lb({{ }}); - 0x1: lh({{ }}); - 0x2: lwl({{ }}); - 0x3: lw({{ }}); - 0x4: lbu({{ }}); - 0x5: lhu({{ }}); - 0x6: lhu({{ }}); - }; - - 0x7: FailUnimpl::reserved({{ }}); - }; - - 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ - 0x0: sb({{ }}); - 0x1: sh({{ }}); - 0x2: swl({{ }}); - 0x3: sw({{ }}); - 0x6: swr({{ }}); - }; - - format FailUnimpl{ - 0x4: reserved({{ }}); - 0x5: reserved({{ }}); - 0x7: cache({{ }}); - }; - - }; - - 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ - 0x0: ll({{ }}); - 0x1: lwc1({{ }}); - 0x5: ldc1({{ }}); - }; - }; - - 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ - 0x0: sc({{ }}); - 0x1: swc1({{ }}); - 0x5: sdc1({{ }}); - }; - - } -} - - diff --git a/arch/mips/isa/formats.h b/arch/mips/isa/formats.def similarity index 100% rename from arch/mips/isa/formats.h rename to arch/mips/isa/formats.def diff --git a/arch/mips/isa/operands.h b/arch/mips/isa/operands.def similarity index 100% rename from arch/mips/isa/operands.h rename to arch/mips/isa/operands.def From 035b443093cc969c79e67285b0f421a7f12edf33 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 3 Feb 2006 23:04:06 -0500 Subject: [PATCH 4/7] mainly added minor support for the basic arithmetic operations (add, mult, shift) arch/mips/isa/bitfields.def: Add comment, move definition up in file arch/mips/isa/decoder.def: add basic arithmetic operations arch/mips/isa/formats/fp.format: change Integer -> FP words arch/mips/isa/formats/int.format: Add derived IntImm class arch/mips/isa/operands.def: change to MIPS sytle operands --HG-- rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15 --- arch/mips/isa/bitfields.def | 8 +- arch/mips/isa/decoder.def | 195 ++++++++++-------- .../isa/formats/{fpop.format => fp.format} | 2 +- .../formats/{integerop.format => int.format} | 26 ++- arch/mips/isa/operands.def | 21 +- 5 files changed, 151 insertions(+), 101 deletions(-) rename arch/mips/isa/formats/{fpop.format => fp.format} (99%) rename arch/mips/isa/formats/{integerop.format => int.format} (83%) diff --git a/arch/mips/isa/bitfields.def b/arch/mips/isa/bitfields.def index 0a94978996..2b5cd62f16 100644 --- a/arch/mips/isa/bitfields.def +++ b/arch/mips/isa/bitfields.def @@ -9,6 +9,7 @@ def bitfield OPCODE_LO <28:26>; def bitfield FUNCTION_HI < 5: 3>; def bitfield FUNCTION_LO < 2: 0>; +// Integer operate format def bitfield RT <20:16>; def bitfield RT_HI <20:19>; def bitfield RT_LO <18:16>; @@ -19,8 +20,10 @@ def bitfield RS_LO <23:21>; def bitfield RD <15:11>; +def bitfield INTIMM <15: 0>; // integer immediate (literal) + // Floating-point operate format -def bitfield FMT <25:21>; +def bitfield FMT <25:21>; def bitfield FT <20:16>; def bitfield FS <15:11>; def bitfield FD <10:6>; @@ -34,9 +37,6 @@ def bitfield SA <10: 6>; // Interrupts def bitfield SC < 5: 5>; -// Integer operate format(s>; -def bitfield INTIMM <15: 0>; // integer immediate (literal) - // Branch format def bitfield OFFSET <15: 0>; // displacement diff --git a/arch/mips/isa/decoder.def b/arch/mips/isa/decoder.def index 49066c9bf8..8453b542ca 100644 --- a/arch/mips/isa/decoder.def +++ b/arch/mips/isa/decoder.def @@ -18,31 +18,37 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format Move { - 0: movc({{ }}); - 1: movt({{ }}); + 0: movf({{ if( FPConditionCode(CC) == 0) Rd = Rs}}); + 1: movt({{ if( FPConditionCode(CC) == 1) Rd = Rs}}); } } - format ShiftRotate { + format BasicOp { + //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - 0x0: sll({{ }}); + + 0x0: sll({{ Rd = Rt.uw << SA; }}); 0x2: decode SRL { - 0: srl({{ }}); - 1: rotr({{ }}); + 0: srl({{ Rd = Rt.uw >> SA; }}); + + //Hardcoded assuming 32-bit ISA, probably need parameter here + 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); } - 0x3: sar({{ }}); - - 0x4: sllv({{ }}); + 0x3: sra({{ Rd = Rt.sw >> SA; }}); + + 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 0x6: decode SRLV { - 0: srlv({{ }}); - 1: rotrv({{ }}); + 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); + + //Hardcoded assuming 32-bit ISA, probably need parameter here + 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); } - 0x7: srav({{ }}); + 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); } } @@ -51,22 +57,24 @@ decode OPCODE_HI default FailUnimpl::unknown() { //Table A-3 Note: "Specific encodings of the hint field are used //to distinguish JR from JR.HB and JALR from JALR.HB" format Jump { - 0x0: jr({{ }}); - 0x1: jalr({{ }}); + 0x0: jr(IsReturn); + 0x1: jalr(IsCall,IsReturn); } format Move { - 0x2: movz({{ }}); - 0x3: movn({{ }}); + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); } - 0x4: Syscall::syscall({{ }}); - 0x5: Break::break({{ }}); - 0x7: Synchronize::synch({{ }}); + format Trap { + 0x4: Syscall::syscall({{ xc->syscall()}},IsNonSpeculative); + 0x5: Break::break({{ }}); + 0x7: Synchronize::sync({{ }}); + } } 0x2: decode FUNCTION_LO { - format MultDiv { + format IntOp { 0x0: mfhi({{ }}); 0x1: mthi({{ }}); 0x2: mflo({{ }}); @@ -75,34 +83,31 @@ decode OPCODE_HI default FailUnimpl::unknown() { }; 0x3: decode FUNCTION_LO { - format MultDiv { - 0x0: mult({{ }}); - 0x1: multu({{ }}); - 0x2: div({{ }}); - 0x3: divu({{ }}); + format IntOp { + 0x0: mult({{ Rd.sw = Rs.sw * Rt.sw; }}); + 0x1: multu({{ Rd.sw = Rs.uw * Rt.uw;}}); + 0x2: div({{ Rd.sw = Rs.sw / Rt.sw;}}); + 0x3: divu({{ Rd.sw = Rs.sw / Rt.uw;}}); } }; 0x4: decode FUNCTION_LO { - format Arithmetic { - 0x0: add({{ }}); - 0x1: addu({{ }}); - 0x2: sub({{ }}); - 0x3: subu({{ }}); - } - - format Logical { - 0x0: and({{ }}); - 0x1: or({{ }}); - 0x2: xor({{ }}); - 0x3: nor({{ }}); + format IntOp { + 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); + 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); + 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); + 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); + 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); + 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); + 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); + 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); } } 0x5: decode FUNCTION_LO { - format SetInstructions{ - 0x2: slt({{ }}); - 0x3: sltu({{ }}); + format IntOp{ + 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); + 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); } }; @@ -153,13 +158,15 @@ decode OPCODE_HI default FailUnimpl::unknown() { } 0x3: decode REGIMM_LO { - 0x7: synci({{ }}); + format Trap { + 0x7: synci({{ }}); + } } } format Jump { - 0x2: j({{ }}); - 0x3: jal({{ }}); + 0x2: j(); + 0x3: jal(IsCall); } format Branch { @@ -171,14 +178,17 @@ decode OPCODE_HI default FailUnimpl::unknown() { }; 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ - format IntImmediate { - 0x0: addi({{ }}); - 0x1: addiu({{ }}); - 0x2: slti({{ }}); - 0x3: sltiu({{ }}); - 0x4: andi({{ }}); - 0x5: ori({{ }}); - 0x6: xori({{ }}); + format IntOp { + 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); + 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); + 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); + 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); + 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); + 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); + 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); + }; + + format Memory { 0x7: lui({{ }}); }; }; @@ -193,8 +203,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0xA: rdpgpr({{ }}); 0xB: decode SC { - 0x0: di({{ }}); - 0x1: ei({{ }}); + format BasicOp { + 0x0: di({{ }}); + 0x1: ei({{ }}); + } } 0xE: wrpgpr({{ }}); @@ -202,13 +214,18 @@ decode OPCODE_HI default FailUnimpl::unknown() { //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { - 0x01: tlbr({{ }}); - 0x02: tlbwi({{ }}); - 0x06: tlbwr({{ }}); - 0x08: tlbp({{ }}); - 0x18: eret({{ }}); - 0x1F: deret({{ }}); - 0x20: wait({{ }}); + format Trap { + 0x01: tlbr({{ }}); + 0x02: tlbwi({{ }}); + 0x06: tlbwr({{ }}); + 0x08: tlbp({{ }}); + } + + format BasicOp { + 0x18: eret({{ }}); + 0x1F: deret({{ }}); + 0x20: wait({{ }}); + } } } @@ -227,13 +244,17 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: decode ND { 0x0: decode TF { - 0x0: bc1f({{ }}); - 0x1: bc1t({{ }}); + format Branch { + 0x0: bc1f({{ }}); + 0x1: bc1t({{ }}); + } } 0x1: decode TF { - 0x0: bc1fl({{ }}); - 0x1: bc1tl({{ }}); + format Branch { + 0x0: bc1fl({{ }}); + 0x1: bc1tl({{ }}); + } } } } @@ -276,8 +297,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: movt_fmt({{ }}); } - 0x2: movz({{ }}); - 0x3: movn({{ }}); + format Move { + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); + } format mode64 { 0x2: recip({{ }}); @@ -331,8 +354,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: movt_fmt({{ }}); } - 0x2: movz({{ }}); - 0x3: movn({{ }}); + format Move { + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); + } format mode64 { 0x5: recip({{ }}); @@ -384,8 +409,6 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: movt_fmt({{ }}); } - 0x2: movz({{ }}); - 0x3: movn({{ }}); } 0x4: decode RS_LO { @@ -416,13 +439,17 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: decode ND { 0x0: decode TF { - 0x0: bc2f({{ }}); - 0x1: bc2t({{ }}); + format Branch { + 0x0: bc2f({{ }}); + 0x1: bc2t({{ }}); + } } 0x1: decode TF { - 0x0: bc2fl({{ }}); - 0x1: bc2tl({{ }}); + format Branch { + 0x0: bc2fl({{ }}); + 0x1: bc2tl({{ }}); + } } } } @@ -479,7 +506,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x7: bgtzl({{ }}); }; - 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ + 0x3: decode OPCODE_LO default FailUnimpl::reserved() { //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 0x4: decode FUNCTION_HI { @@ -523,8 +550,8 @@ decode OPCODE_HI default FailUnimpl::unknown() { } }; - 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ + 0x4: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { 0x0: lb({{ }}); 0x1: lh({{ }}); 0x2: lwl({{ }}); @@ -537,8 +564,8 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x7: FailUnimpl::reserved({{ }}); }; - 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ + 0x5: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { 0x0: sb({{ }}); 0x1: sh({{ }}); 0x2: swl({{ }}); @@ -546,7 +573,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x6: swr({{ }}); }; - format FailUnimpl{ + format FailUnimpl { 0x4: reserved({{ }}); 0x5: reserved({{ }}); 0x7: cache({{ }}); @@ -554,16 +581,16 @@ decode OPCODE_HI default FailUnimpl::unknown() { }; - 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ - format LoadMemory{ + 0x6: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { 0x0: ll({{ }}); 0x1: lwc1({{ }}); 0x5: ldc1({{ }}); }; }; - 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ - format StoreMemory{ + 0x7: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { 0x0: sc({{ }}); 0x1: swc1({{ }}); 0x5: sdc1({{ }}); diff --git a/arch/mips/isa/formats/fpop.format b/arch/mips/isa/formats/fp.format similarity index 99% rename from arch/mips/isa/formats/fpop.format rename to arch/mips/isa/formats/fp.format index a058eea19f..707109fc28 100644 --- a/arch/mips/isa/formats/fpop.format +++ b/arch/mips/isa/formats/fp.format @@ -27,7 +27,7 @@ output decoder {{ } }}; -def template IntegerExecute {{ +def template FPExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { //These are set to constants when the execute method diff --git a/arch/mips/isa/formats/integerop.format b/arch/mips/isa/formats/int.format similarity index 83% rename from arch/mips/isa/formats/integerop.format rename to arch/mips/isa/formats/int.format index 6fa7feed3d..9b2d8d38e9 100644 --- a/arch/mips/isa/formats/integerop.format +++ b/arch/mips/isa/formats/int.format @@ -7,7 +7,7 @@ output header {{ /** * Base class for integer operations. */ - class IntegerOp : public MipsStaticInst + class IntOp : public MipsStaticInst { protected: @@ -18,16 +18,36 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + /** + * Derived class for integer immediate operations. + */ + class IntImm : public IntOp + { + protected: + + /// Constructor + IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; }}; output decoder {{ - std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return "Disassembly of integer instruction\n"; } + + std::string IntImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer immediate instruction\n"; + } }}; -def template IntegerExecute {{ +def template IntExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { //These are set to constants when the execute method diff --git a/arch/mips/isa/operands.def b/arch/mips/isa/operands.def index 77de6c9c44..16d8fbceb4 100644 --- a/arch/mips/isa/operands.def +++ b/arch/mips/isa/operands.def @@ -13,17 +13,20 @@ def operand_types {{ }}; def operands {{ - # Int regs default to unsigned, but code should not count on this. - # For clarity, descriptions that depend on unsigned behavior should - # explicitly specify '.uq'. - 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), - 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), - 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), - #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), - #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), - #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), + 'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1), + 'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2), + 'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3), + + 'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3), + 'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4), + + 'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1), + 'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2), + 'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3), + 'Mem': MemOperandTraits('udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), From 6d2807ded8660f241aaecd28ff716c1d91f8b5a0 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sat, 4 Feb 2006 18:59:44 -0500 Subject: [PATCH 5/7] 1st full draft switch statement actions for all integer arithmetic operations and the majority of the load & store operations (not all of FP-Ops), Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ... --HG-- extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356 --- arch/mips/isa/decoder.def | 167 ++++++++++++++++++++++++-------------- 1 file changed, 104 insertions(+), 63 deletions(-) diff --git a/arch/mips/isa/decoder.def b/arch/mips/isa/decoder.def index 8453b542ca..878c90ca53 100644 --- a/arch/mips/isa/decoder.def +++ b/arch/mips/isa/decoder.def @@ -18,8 +18,8 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format Move { - 0: movf({{ if( FPConditionCode(CC) == 0) Rd = Rs}}); - 1: movt({{ if( FPConditionCode(CC) == 1) Rd = Rs}}); + 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); + 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); } } @@ -67,27 +67,45 @@ decode OPCODE_HI default FailUnimpl::unknown() { } format Trap { - 0x4: Syscall::syscall({{ xc->syscall()}},IsNonSpeculative); - 0x5: Break::break({{ }}); - 0x7: Synchronize::sync({{ }}); + 0x4: syscall({{ xc->syscall()}},IsNonSpeculative); + 0x5: break({{ }}); + 0x7: sync({{ }}); } } 0x2: decode FUNCTION_LO { - format IntOp { - 0x0: mfhi({{ }}); - 0x1: mthi({{ }}); - 0x2: mflo({{ }}); - 0x3: mtlo({{ }}); + format BasicOp { + 0x0: mfhi({{ Rd = xc->miscRegs.Hi; }}); + 0x1: mthi({{ xc->miscRegs.Hi = Rs; }}); + 0x2: mflo({{ Rd = xc->miscRegs.Lo; }}); + 0x3: mtlo({{ xc->miscRegs.Lo = Rs; }}); } }; 0x3: decode FUNCTION_LO { format IntOp { - 0x0: mult({{ Rd.sw = Rs.sw * Rt.sw; }}); - 0x1: multu({{ Rd.sw = Rs.uw * Rt.uw;}}); - 0x2: div({{ Rd.sw = Rs.sw / Rt.sw;}}); - 0x3: divu({{ Rd.sw = Rs.sw / Rt.uw;}}); + 0x0: mult({{ + INT64 temp1 = Rs.sw * Rt.sw; + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x1: multu({{ + INT64 temp1 = Rs.uw * Rt.uw; + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + Rd.sw = Rs.uw * Rt.uw; + }}); + + 0x2: div({{ + xc->miscRegs.Hi = Rs.sw % Rt.sw; + xc->miscRegs.Lo = Rs.sw / Rt.sw; + }}); + + 0x3: divu({{ + xc->miscRegs.Hi = Rs.uw % Rt.uw; + xc->miscRegs.Lo = Rs.uw / Rt.uw; + }}); } }; @@ -126,12 +144,12 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: decode REGIMM_HI { 0x0: decode REGIMM_LO { format Branch { - 0x0: bltz({{ }}); - 0x1: bgez({{ }}); + 0x0: bltz({{ cond = (Rs.sq < 0); }}); + 0x1: bgez({{ cond = (Rs.sq >= 0); }}); //MIPS obsolete instructions - 0x2: bltzl({{ }}); - 0x3: bgezl({{ }}); + 0x2: bltzl({{ cond = (Rs.sq < 0); }}); + 0x3: bgezl({{ cond = (Rs.sq >= 0); }}); } } @@ -148,12 +166,12 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x2: decode REGIMM_LO { format Branch { - 0x0: bltzal({{ }}); - 0x1: bgezal({{ }}); + 0x0: bltzal({{ cond = (Rs.sq < 0); }}); + 0x1: bgezal({{ cond = (Rs.sq >= 0); }}); //MIPS obsolete instructions - 0x2: bltzall({{ }}); - 0x3: bgezall({{ }}); + 0x2: bltzall({{ cond = (Rs.sq < 0); }}); + 0x3: bgezall({{ cond = (Rs.sq >= 0); }}); } } @@ -170,10 +188,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { } format Branch { - 0x4: beq({{ }}); - 0x5: bne({{ }}); - 0x6: blez({{ }}); - 0x7: bgtz({{ }}); + 0x4: beq({{ cond = (Rs.sq == 0); }}); + 0x5: bne({{ cond = (Rs.sq != 0); }}); + 0x6: blez({{ cond = (Rs.sq <= 0); }}); + 0x7: bgtz({{ cond = (Rs.sq > 0); }}); } }; @@ -186,10 +204,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); - }; - - format Memory { - 0x7: lui({{ }}); + 0x7: lui({{ Rt = INTIMM << 16}}); }; }; @@ -245,15 +260,15 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: decode ND { 0x0: decode TF { format Branch { - 0x0: bc1f({{ }}); - 0x1: bc1t({{ }}); + 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); + 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); } } 0x1: decode TF { format Branch { - 0x0: bc1fl({{ }}); - 0x1: bc1tl({{ }}); + 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); + 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); } } } @@ -440,15 +455,15 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: decode ND { 0x0: decode TF { format Branch { - 0x0: bc2f({{ }}); - 0x1: bc2t({{ }}); + 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2); + 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); } } 0x1: decode TF { format Branch { - 0x0: bc2fl({{ }}); - 0x1: bc2tl({{ }}); + 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}}); + 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); } } } @@ -500,10 +515,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { } //MIPS obsolete instructions - 0x4: beql({{ }}); - 0x5: bnel({{ }}); - 0x6: blezl({{ }}); - 0x7: bgtzl({{ }}); + 0x4: beql({{ cond = (Rs.sq == 0); }}); + 0x5: bnel({{ cond = (Rs.sq != 0); }}); + 0x6: blezl({{ cond = (Rs.sq <= 0); }}); + 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); }; 0x3: decode OPCODE_LO default FailUnimpl::reserved() { @@ -512,11 +527,37 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x4: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - 0x0: madd({{ }}); - 0x1: maddu({{ }}); - 0x2: mult({{ }}); - 0x4: msub({{ }}); - 0x5: msubu({{ }}); + format IntOp { + 0x0: madd({{ + INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + temp1 = temp1 + (Rs.sw * Rt.sw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x1: maddu({{ + INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + temp1 = temp1 + (Rs.uw * Rt.uw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); + + 0x4: msub({{ + INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + temp1 = temp1 - (Rs.sw * Rt.sw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x5: msubu({{ + INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + temp1 = temp1 - (Rs.uw * Rt.uw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + } } 0x4: decode FUNCTION_LO { @@ -552,13 +593,13 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x4: decode OPCODE_LO default FailUnimpl::reserved() { format Memory { - 0x0: lb({{ }}); - 0x1: lh({{ }}); - 0x2: lwl({{ }}); - 0x3: lw({{ }}); - 0x4: lbu({{ }}); - 0x5: lhu({{ }}); - 0x6: lhu({{ }}); + 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); + 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); + 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign); + 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); + 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); + 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); + 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign); }; 0x7: FailUnimpl::reserved({{ }}); @@ -566,11 +607,11 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x5: decode OPCODE_LO default FailUnimpl::reserved() { format Memory { - 0x0: sb({{ }}); - 0x1: sh({{ }}); - 0x2: swl({{ }}); - 0x3: sw({{ }}); - 0x6: swr({{ }}); + 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); + 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); + 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); + 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); + 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); }; format FailUnimpl { @@ -584,16 +625,16 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x6: decode OPCODE_LO default FailUnimpl::reserved() { format Memory { 0x0: ll({{ }}); - 0x1: lwc1({{ }}); - 0x5: ldc1({{ }}); + 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); + 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); }; }; 0x7: decode OPCODE_LO default FailUnimpl::reserved() { format Memory { 0x0: sc({{ }}); - 0x1: swc1({{ }}); - 0x5: sdc1({{ }}); + 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); + 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); }; } From d30262d480b8a167470c17a35aecc727ea933a22 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 7 Feb 2006 18:36:08 -0500 Subject: [PATCH 6/7] name changes ... minor IntOP format change arch/mips/isa/formats/int.format: Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from their reg-reg counterparts --HG-- rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc --- .../mips/isa/{bitfields.def => bitfields.isa} | 8 +- arch/mips/isa/decoder.def | 643 ------------------ arch/mips/isa/decoder.isa | 643 ++++++++++++++++++ arch/mips/isa/{formats.def => formats.isa} | 0 arch/mips/isa/formats/int.format | 65 +- arch/mips/isa/{includes.h => includes.isa} | 0 arch/mips/isa/{operands.def => operands.isa} | 4 +- 7 files changed, 652 insertions(+), 711 deletions(-) rename arch/mips/isa/{bitfields.def => bitfields.isa} (88%) delete mode 100644 arch/mips/isa/decoder.def create mode 100644 arch/mips/isa/decoder.isa rename arch/mips/isa/{formats.def => formats.isa} (100%) rename arch/mips/isa/{includes.h => includes.isa} (100%) rename arch/mips/isa/{operands.def => operands.isa} (94%) diff --git a/arch/mips/isa/bitfields.def b/arch/mips/isa/bitfields.isa similarity index 88% rename from arch/mips/isa/bitfields.def rename to arch/mips/isa/bitfields.isa index 2b5cd62f16..94a8a64676 100644 --- a/arch/mips/isa/bitfields.def +++ b/arch/mips/isa/bitfields.isa @@ -41,11 +41,11 @@ def bitfield SC < 5: 5>; def bitfield OFFSET <15: 0>; // displacement // Memory-format jumps -def bitfield JMPTARG <25: 0>; -def bitfield JMPHINT <10: 6>; +def bitfield JMPTARG <25: 0>; +def bitfield JMPHINT <10: 6>; -def bitfield SYSCALLCODE <25: 6>; -def bitfield TRAPCODE <15:13>; +def bitfield SYSCALLCODE <25: 6>; +def bitfield TRAPCODE <15:13>; // M5 instructions def bitfield M5FUNC <7:0>; diff --git a/arch/mips/isa/decoder.def b/arch/mips/isa/decoder.def deleted file mode 100644 index 878c90ca53..0000000000 --- a/arch/mips/isa/decoder.def +++ /dev/null @@ -1,643 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// The actual MIPS32 ISA decoder -// ----------------------------- -// The following instructions are specified in the MIPS32 ISA -// Specification. Decoding closely follows the style specified -// in the MIPS32 ISAthe specification document starting with Table -// A-2 (document available @ www.mips.com) -// -//@todo: Distinguish "unknown/future" use insts from "reserved" -// ones -decode OPCODE_HI default FailUnimpl::unknown() { - - // Derived From ... Table A-2 MIPS32 ISA Manual - 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ - - 0x0: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x1: decode MOVCI { - format Move { - 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); - 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); - } - } - - format BasicOp { - - //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields - //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - - 0x0: sll({{ Rd = Rt.uw << SA; }}); - - 0x2: decode SRL { - 0: srl({{ Rd = Rt.uw >> SA; }}); - - //Hardcoded assuming 32-bit ISA, probably need parameter here - 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); - } - - 0x3: sra({{ Rd = Rt.sw >> SA; }}); - - 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); - - 0x6: decode SRLV { - 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); - - //Hardcoded assuming 32-bit ISA, probably need parameter here - 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); - } - - 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); - } - } - - 0x1: decode FUNCTION_LO { - - //Table A-3 Note: "Specific encodings of the hint field are used - //to distinguish JR from JR.HB and JALR from JALR.HB" - format Jump { - 0x0: jr(IsReturn); - 0x1: jalr(IsCall,IsReturn); - } - - format Move { - 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); - 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); - } - - format Trap { - 0x4: syscall({{ xc->syscall()}},IsNonSpeculative); - 0x5: break({{ }}); - 0x7: sync({{ }}); - } - } - - 0x2: decode FUNCTION_LO { - format BasicOp { - 0x0: mfhi({{ Rd = xc->miscRegs.Hi; }}); - 0x1: mthi({{ xc->miscRegs.Hi = Rs; }}); - 0x2: mflo({{ Rd = xc->miscRegs.Lo; }}); - 0x3: mtlo({{ xc->miscRegs.Lo = Rs; }}); - } - }; - - 0x3: decode FUNCTION_LO { - format IntOp { - 0x0: mult({{ - INT64 temp1 = Rs.sw * Rt.sw; - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - }}); - - 0x1: multu({{ - INT64 temp1 = Rs.uw * Rt.uw; - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - Rd.sw = Rs.uw * Rt.uw; - }}); - - 0x2: div({{ - xc->miscRegs.Hi = Rs.sw % Rt.sw; - xc->miscRegs.Lo = Rs.sw / Rt.sw; - }}); - - 0x3: divu({{ - xc->miscRegs.Hi = Rs.uw % Rt.uw; - xc->miscRegs.Lo = Rs.uw / Rt.uw; - }}); - } - }; - - 0x4: decode FUNCTION_LO { - format IntOp { - 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); - 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); - 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); - 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); - 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); - 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); - 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); - 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); - } - } - - 0x5: decode FUNCTION_LO { - format IntOp{ - 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); - 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); - } - }; - - 0x6: decode FUNCTION_LO { - format Trap { - 0x0: tge({{ }}); - 0x1: tgeu({{ }}); - 0x2: tlt({{ }}); - 0x3: tltu({{ }}); - 0x4: teq({{ }}); - 0x6: tne({{ }}); - } - } - } - - 0x1: decode REGIMM_HI { - 0x0: decode REGIMM_LO { - format Branch { - 0x0: bltz({{ cond = (Rs.sq < 0); }}); - 0x1: bgez({{ cond = (Rs.sq >= 0); }}); - - //MIPS obsolete instructions - 0x2: bltzl({{ cond = (Rs.sq < 0); }}); - 0x3: bgezl({{ cond = (Rs.sq >= 0); }}); - } - } - - 0x1: decode REGIMM_LO { - format Trap { - 0x0: tgei({{ }}); - 0x1: tgeiu({{ }}); - 0x2: tlti({{ }}); - 0x3: tltiu({{ }}); - 0x4: teqi({{ }}); - 0x6: tnei({{ }}); - } - } - - 0x2: decode REGIMM_LO { - format Branch { - 0x0: bltzal({{ cond = (Rs.sq < 0); }}); - 0x1: bgezal({{ cond = (Rs.sq >= 0); }}); - - //MIPS obsolete instructions - 0x2: bltzall({{ cond = (Rs.sq < 0); }}); - 0x3: bgezall({{ cond = (Rs.sq >= 0); }}); - } - } - - 0x3: decode REGIMM_LO { - format Trap { - 0x7: synci({{ }}); - } - } - } - - format Jump { - 0x2: j(); - 0x3: jal(IsCall); - } - - format Branch { - 0x4: beq({{ cond = (Rs.sq == 0); }}); - 0x5: bne({{ cond = (Rs.sq != 0); }}); - 0x6: blez({{ cond = (Rs.sq <= 0); }}); - 0x7: bgtz({{ cond = (Rs.sq > 0); }}); - } - }; - - 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ - format IntOp { - 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); - 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); - 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); - 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); - 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); - 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); - 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); - 0x7: lui({{ Rt = INTIMM << 16}}); - }; - }; - - 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ - - //Table A-11 MIPS32 COP0 Encoding of rs Field - 0x0: decode RS_MSB { - 0x0: decode RS { - 0x0: mfc0({{ }}); - 0xC: mtc0({{ }}); - 0xA: rdpgpr({{ }}); - - 0xB: decode SC { - format BasicOp { - 0x0: di({{ }}); - 0x1: ei({{ }}); - } - } - - 0xE: wrpgpr({{ }}); - } - - //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO - 0x1: decode FUNCTION { - format Trap { - 0x01: tlbr({{ }}); - 0x02: tlbwi({{ }}); - 0x06: tlbwr({{ }}); - 0x08: tlbp({{ }}); - } - - format BasicOp { - 0x18: eret({{ }}); - 0x1F: deret({{ }}); - 0x20: wait({{ }}); - } - } - } - - //Table A-13 MIPS32 COP1 Encoding of rs Field - 0x1: decode RS_MSB { - - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc1({{ }}); - 0x2: cfc1({{ }}); - 0x3: mfhc1({{ }}); - 0x4: mtc1({{ }}); - 0x6: ctc1({{ }}); - 0x7: mftc1({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - format Branch { - 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); - 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); - } - } - - 0x1: decode TF { - format Branch { - 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); - 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); - } - } - } - } - - 0x1: decode RS_HI { - 0x2: decode RS_LO { - - //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S - //(( single-word )) - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - format Move { - 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); - 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); - } - - format mode64 { - 0x2: recip({{ }}); - 0x3: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x1: cvt_d({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - 0x6: cvt_ps({{ }}); - } - } - } - - //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D - 0x1: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x1: decode RS_LO { - //only legal for 64 bit - format mode64 { - 0x0: round_l({{ }}); - 0x1: trunc_l({{ }}); - 0x2: ceil_l({{ }}); - 0x3: floor_l({{ }}); - } - - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - format Move { - 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); - 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); - } - - format mode64 { - 0x5: recip({{ }}); - 0x6: rsqrt{{ }}); - } - } - - 0x4: decode RS_LO { - 0x0: cvt_s({{ }}); - 0x4: cvt_w({{ }}); - - //only legal for 64 bit - format mode64 { - 0x5: cvt_l({{ }}); - } - } - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W - 0x4: decode FUNCTION { - 0x10: cvt_s({{ }}); - 0x10: cvt_d({{ }}); - } - - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 - //Note: "1. Format type L is legal only if 64-bit floating point operations - //are enabled." - 0x5: decode FUNCTION_HI { - 0x10: cvt_s({{ }}); - 0x11: cvt_d({{ }}); - } - - //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 - //Note: "1. Format type PS is legal only if 64-bit floating point operations - //are enabled. " - 0x6: decode RS_HI { - 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); - } - - 0x2: decode RS_LO { - 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); - } - - } - - 0x4: decode RS_LO { - 0x0: cvt_s_pu({{ }}); - } - - 0x5: decode RS_LO { - 0x0: cvt_s_pl({{ }}); - 0x4: pll_s_pl({{ }}); - 0x5: plu_s_pl({{ }}); - 0x6: pul_s_pl({{ }}); - 0x7: puu_s_pl({{ }}); - } - } - } - - //Table A-19 MIPS32 COP2 Encoding of rs Field - 0x2: decode RS_MSB { - 0x0: decode RS_HI { - 0x0: decode RS_LO { - 0x0: mfc2({{ }}); - 0x2: cfc2({{ }}); - 0x3: mfhc2({{ }}); - 0x4: mtc2({{ }}); - 0x6: ctc2({{ }}); - 0x7: mftc2({{ }}); - } - - 0x1: decode ND { - 0x0: decode TF { - format Branch { - 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2); - 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); - } - } - - 0x1: decode TF { - format Branch { - 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}}); - 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); - } - } - } - } - } - - //Table A-20 MIPS64 COP1X Encoding of Function Field 1 - //Note: "COP1X instructions are legal only if 64-bit floating point - //operations are enabled." - 0x3: decode FUNCTION_HI { - 0x0: decode FUNCTION_LO { - 0x0: lwxc1({{ }}); - 0x1: ldxc1({{ }}); - 0x5: luxc1({{ }}); - } - - 0x1: decode FUNCTION_LO { - 0x0: swxc1({{ }}); - 0x1: sdxc1({{ }}); - 0x5: suxc1({{ }}); - 0x7: prefx({{ }}); - } - - 0x3: alnv_ps({{ }}); - - 0x4: decode FUNCTION_LO { - 0x0: madd_s({{ }}); - 0x1: madd_d({{ }}); - 0x6: madd_ps({{ }}); - } - - 0x5: decode FUNCTION_LO { - 0x0: msub_s({{ }}); - 0x1: msub_d({{ }}); - 0x6: msub_ps({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x0: nmadd_s({{ }}); - 0x1: nmadd_d({{ }}); - 0x6: nmadd_ps({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x0: nmsub_s({{ }}); - 0x1: nmsub_d({{ }}); - 0x6: nmsub_ps({{ }}); - } - } - - //MIPS obsolete instructions - 0x4: beql({{ cond = (Rs.sq == 0); }}); - 0x5: bnel({{ cond = (Rs.sq != 0); }}); - 0x6: blezl({{ cond = (Rs.sq <= 0); }}); - 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); - }; - - 0x3: decode OPCODE_LO default FailUnimpl::reserved() { - - //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field - 0x4: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - format IntOp { - 0x0: madd({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; - temp1 = temp1 + (Rs.sw * Rt.sw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - }}); - - 0x1: maddu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; - temp1 = temp1 + (Rs.uw * Rt.uw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - }}); - - 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); - - 0x4: msub({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; - temp1 = temp1 - (Rs.sw * Rt.sw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - }}); - - 0x5: msubu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; - temp1 = temp1 - (Rs.uw * Rt.uw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> - }}); - } - } - - 0x4: decode FUNCTION_LO { - 0x0: clz({{ }}); - 0x1: clo({{ }}); - } - - 0x7: decode FUNCTION_LO { - 0x7: sdbbp({{ }}); - } - } - - //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture - 0x7: decode FUNCTION_HI { - - 0x0: decode FUNCTION_LO { - 0x1: ext({{ }}); - 0x4: ins({{ }}); - } - - //Table A-10 MIPS32 BSHFL Encoding of sa Field - 0x4: decode SA { - 0x02: wsbh({{ }}); - 0x10: seb({{ }}); - 0x18: seh({{ }}); - } - - 0x6: decode FUNCTION_LO { - 0x7: rdhwr({{ }}); - } - } - }; - - 0x4: decode OPCODE_LO default FailUnimpl::reserved() { - format Memory { - 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); - 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); - 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign); - 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); - 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); - 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); - 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign); - }; - - 0x7: FailUnimpl::reserved({{ }}); - }; - - 0x5: decode OPCODE_LO default FailUnimpl::reserved() { - format Memory { - 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); - 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); - 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); - 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); - 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); - }; - - format FailUnimpl { - 0x4: reserved({{ }}); - 0x5: reserved({{ }}); - 0x7: cache({{ }}); - }; - - }; - - 0x6: decode OPCODE_LO default FailUnimpl::reserved() { - format Memory { - 0x0: ll({{ }}); - 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); - 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); - }; - }; - - 0x7: decode OPCODE_LO default FailUnimpl::reserved() { - format Memory { - 0x0: sc({{ }}); - 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); - 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); - }; - - } -} - - diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa new file mode 100644 index 0000000000..f0c3fc5622 --- /dev/null +++ b/arch/mips/isa/decoder.isa @@ -0,0 +1,643 @@ +//////////////////////////////////////////////////////////////////// +// +// The actual MIPS32 ISA decoder +// ----------------------------- +// The following instructions are specified in the MIPS32 ISA +// Specification. Decoding closely follows the style specified +// in the MIPS32 ISAthe specification document starting with Table +// A-2 (document available @ www.mips.com) +// +//@todo: Distinguish "unknown/future" use insts from "reserved" +// ones +decode OPCODE_HI default FailUnimpl::unknown() { + + // Derived From ... Table A-2 MIPS32 ISA Manual + 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ + + 0x0: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x1: decode MOVCI { + format Move { + 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); + 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); + } + } + + format BasicOp { + + //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields + //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." + + 0x0: sll({{ Rd = Rt.uw << SA; }}); + + 0x2: decode SRL { + 0: srl({{ Rd = Rt.uw >> SA; }}); + + //Hardcoded assuming 32-bit ISA, probably need parameter here + 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); + } + + 0x3: sra({{ Rd = Rt.sw >> SA; }}); + + 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); + + 0x6: decode SRLV { + 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); + + //Hardcoded assuming 32-bit ISA, probably need parameter here + 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); + } + + 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); + } + } + + 0x1: decode FUNCTION_LO { + + //Table A-3 Note: "Specific encodings of the hint field are used + //to distinguish JR from JR.HB and JALR from JALR.HB" + format Jump { + 0x0: jr(IsReturn); + 0x1: jalr(IsCall,IsReturn); + } + + format Move { + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); + } + + format Trap { + 0x4: syscall({{ xc->syscall()}},IsNonSpeculative); + 0x5: break({{ }}); + 0x7: sync({{ }}); + } + } + + 0x2: decode FUNCTION_LO { + format BasicOp { + 0x0: mfhi({{ Rd = xc->miscRegs.Hi; }}); + 0x1: mthi({{ xc->miscRegs.Hi = Rs; }}); + 0x2: mflo({{ Rd = xc->miscRegs.Lo; }}); + 0x3: mtlo({{ xc->miscRegs.Lo = Rs; }}); + } + }; + + 0x3: decode FUNCTION_LO { + format IntOp { + 0x0: mult({{ + INT64 temp1 = Rs.sw * Rt.sw; + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x1: multu({{ + INT64 temp1 = Rs.uw * Rt.uw; + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + Rd.sw = Rs.uw * Rt.uw; + }}); + + 0x2: div({{ + xc->miscRegs.Hi = Rs.sw % Rt.sw; + xc->miscRegs.Lo = Rs.sw / Rt.sw; + }}); + + 0x3: divu({{ + xc->miscRegs.Hi = Rs.uw % Rt.uw; + xc->miscRegs.Lo = Rs.uw / Rt.uw; + }}); + } + }; + + 0x4: decode FUNCTION_LO { + format IntOp { + 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); + 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); + 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); + 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); + 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); + 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); + 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); + 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); + } + } + + 0x5: decode FUNCTION_LO { + format IntOp{ + 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); + 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); + } + }; + + 0x6: decode FUNCTION_LO { + format Trap { + 0x0: tge({{ }}); + 0x1: tgeu({{ }}); + 0x2: tlt({{ }}); + 0x3: tltu({{ }}); + 0x4: teq({{ }}); + 0x6: tne({{ }}); + } + } + } + + 0x1: decode REGIMM_HI { + 0x0: decode REGIMM_LO { + format Branch { + 0x0: bltz({{ cond = (Rs.sq < 0); }}); + 0x1: bgez({{ cond = (Rs.sq >= 0); }}); + + //MIPS obsolete instructions + 0x2: bltzl({{ cond = (Rs.sq < 0); }}); + 0x3: bgezl({{ cond = (Rs.sq >= 0); }}); + } + } + + 0x1: decode REGIMM_LO { + format Trap { + 0x0: tgei({{ }}); + 0x1: tgeiu({{ }}); + 0x2: tlti({{ }}); + 0x3: tltiu({{ }}); + 0x4: teqi({{ }}); + 0x6: tnei({{ }}); + } + } + + 0x2: decode REGIMM_LO { + format Branch { + 0x0: bltzal({{ cond = (Rs.sq < 0); }}); + 0x1: bgezal({{ cond = (Rs.sq >= 0); }}); + + //MIPS obsolete instructions + 0x2: bltzall({{ cond = (Rs.sq < 0); }}); + 0x3: bgezall({{ cond = (Rs.sq >= 0); }}); + } + } + + 0x3: decode REGIMM_LO { + format Trap { + 0x7: synci({{ }}); + } + } + } + + format Jump { + 0x2: j(); + 0x3: jal(IsCall); + } + + format Branch { + 0x4: beq({{ cond = (Rs.sq == 0); }}); + 0x5: bne({{ cond = (Rs.sq != 0); }}); + 0x6: blez({{ cond = (Rs.sq <= 0); }}); + 0x7: bgtz({{ cond = (Rs.sq > 0); }}); + } + }; + + 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ + format IntOp { + 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); + 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); + 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); + 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); + 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); + 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); + 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); + 0x7: lui({{ Rt = INTIMM << 16}}); + }; + }; + + 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-11 MIPS32 COP0 Encoding of rs Field + 0x0: decode RS_MSB { + 0x0: decode RS { + 0x0: mfc0({{ }}); + 0xC: mtc0({{ }}); + 0xA: rdpgpr({{ }}); + + 0xB: decode SC { + format BasicOp { + 0x0: di({{ }}); + 0x1: ei({{ }}); + } + } + + 0xE: wrpgpr({{ }}); + } + + //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO + 0x1: decode FUNCTION { + format Trap { + 0x01: tlbr({{ }}); + 0x02: tlbwi({{ }}); + 0x06: tlbwr({{ }}); + 0x08: tlbp({{ }}); + } + + format BasicOp { + 0x18: eret({{ }}); + 0x1F: deret({{ }}); + 0x20: wait({{ }}); + } + } + } + + //Table A-13 MIPS32 COP1 Encoding of rs Field + 0x1: decode RS_MSB { + + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc1({{ }}); + 0x2: cfc1({{ }}); + 0x3: mfhc1({{ }}); + 0x4: mtc1({{ }}); + 0x6: ctc1({{ }}); + 0x7: mftc1({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + format Branch { + 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); + 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); + } + } + + 0x1: decode TF { + format Branch { + 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); + 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); + } + } + } + } + + 0x1: decode RS_HI { + 0x2: decode RS_LO { + + //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S + //(( single-word )) + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + format Move { + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); + } + + format mode64 { + 0x2: recip({{ }}); + 0x3: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x1: cvt_d({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + 0x6: cvt_ps({{ }}); + } + } + } + + //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D + 0x1: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + format Move { + 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); + 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); + } + + format mode64 { + 0x5: recip({{ }}); + 0x6: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x0: cvt_s({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + } + } + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W + 0x4: decode FUNCTION { + 0x10: cvt_s({{ }}); + 0x10: cvt_d({{ }}); + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 + //Note: "1. Format type L is legal only if 64-bit floating point operations + //are enabled." + 0x5: decode FUNCTION_HI { + 0x10: cvt_s({{ }}); + 0x11: cvt_d({{ }}); + } + + //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 + //Note: "1. Format type PS is legal only if 64-bit floating point operations + //are enabled. " + 0x6: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + } + + 0x4: decode RS_LO { + 0x0: cvt_s_pu({{ }}); + } + + 0x5: decode RS_LO { + 0x0: cvt_s_pl({{ }}); + 0x4: pll_s_pl({{ }}); + 0x5: plu_s_pl({{ }}); + 0x6: pul_s_pl({{ }}); + 0x7: puu_s_pl({{ }}); + } + } + } + + //Table A-19 MIPS32 COP2 Encoding of rs Field + 0x2: decode RS_MSB { + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc2({{ }}); + 0x2: cfc2({{ }}); + 0x3: mfhc2({{ }}); + 0x4: mtc2({{ }}); + 0x6: ctc2({{ }}); + 0x7: mftc2({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + format Branch { + 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2); + 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); + } + } + + 0x1: decode TF { + format Branch { + 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}}); + 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); + } + } + } + } + } + + //Table A-20 MIPS64 COP1X Encoding of Function Field 1 + //Note: "COP1X instructions are legal only if 64-bit floating point + //operations are enabled." + 0x3: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x0: lwxc1({{ }}); + 0x1: ldxc1({{ }}); + 0x5: luxc1({{ }}); + } + + 0x1: decode FUNCTION_LO { + 0x0: swxc1({{ }}); + 0x1: sdxc1({{ }}); + 0x5: suxc1({{ }}); + 0x7: prefx({{ }}); + } + + 0x3: alnv_ps({{ }}); + + 0x4: decode FUNCTION_LO { + 0x0: madd_s({{ }}); + 0x1: madd_d({{ }}); + 0x6: madd_ps({{ }}); + } + + 0x5: decode FUNCTION_LO { + 0x0: msub_s({{ }}); + 0x1: msub_d({{ }}); + 0x6: msub_ps({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x0: nmadd_s({{ }}); + 0x1: nmadd_d({{ }}); + 0x6: nmadd_ps({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x0: nmsub_s({{ }}); + 0x1: nmsub_d({{ }}); + 0x6: nmsub_ps({{ }}); + } + } + + //MIPS obsolete instructions + 0x4: beql({{ cond = (Rs.sq == 0); }}); + 0x5: bnel({{ cond = (Rs.sq != 0); }}); + 0x6: blezl({{ cond = (Rs.sq <= 0); }}); + 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); + }; + + 0x3: decode OPCODE_LO default FailUnimpl::reserved() { + + //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field + 0x4: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + format IntOp { + 0x0: madd({{ + INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + temp1 = temp1 + (Rs.sw * Rt.sw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x1: maddu({{ + INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + temp1 = temp1 + (Rs.uw * Rt.uw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); + + 0x4: msub({{ + INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + temp1 = temp1 - (Rs.sw * Rt.sw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + + 0x5: msubu({{ + INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + temp1 = temp1 - (Rs.uw * Rt.uw); + xc->miscRegs.Hi->temp1<63:32>; + xc->miscRegs.Lo->temp1<31:0> + }}); + } + } + + 0x4: decode FUNCTION_LO { + 0x0: clz({{ }}); + 0x1: clo({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x7: sdbbp({{ }}); + } + } + + //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture + 0x7: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x1: ext({{ }}); + 0x4: ins({{ }}); + } + + //Table A-10 MIPS32 BSHFL Encoding of sa Field + 0x4: decode SA { + 0x02: wsbh({{ }}); + 0x10: seb({{ }}); + 0x18: seh({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x7: rdhwr({{ }}); + } + } + }; + + 0x4: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { + 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); + 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); + 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign); + 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); + 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); + 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); + 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign); + }; + + 0x7: FailUnimpl::reserved({{ }}); + }; + + 0x5: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { + 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); + 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); + 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); + 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); + 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); + }; + + format FailUnimpl { + 0x4: reserved({{ }}); + 0x5: reserved({{ }}); + 0x7: cache({{ }}); + }; + + }; + + 0x6: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { + 0x0: ll({{ }}); + 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); + 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); + }; + }; + + 0x7: decode OPCODE_LO default FailUnimpl::reserved() { + format Memory { + 0x0: sc({{ }}); + 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); + 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); + }; + + } +} + + diff --git a/arch/mips/isa/formats.def b/arch/mips/isa/formats.isa similarity index 100% rename from arch/mips/isa/formats.def rename to arch/mips/isa/formats.isa diff --git a/arch/mips/isa/formats/int.format b/arch/mips/isa/formats/int.format index 9b2d8d38e9..edfdddb18d 100644 --- a/arch/mips/isa/formats/int.format +++ b/arch/mips/isa/formats/int.format @@ -19,20 +19,6 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; - /** - * Derived class for integer immediate operations. - */ - class IntImm : public IntOp - { - protected: - - /// Constructor - IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; }}; output decoder {{ @@ -41,7 +27,7 @@ output decoder {{ return "Disassembly of integer instruction\n"; } - std::string IntImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return "Disassembly of integer immediate instruction\n"; } @@ -50,16 +36,9 @@ output decoder {{ def template IntExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //These are set to constants when the execute method - //is generated - bool useCc = ; - bool checkPriv = ; - //Attempt to execute the instruction try { - checkPriv; - %(op_decl)s; %(op_rd)s; %(code)s; @@ -74,34 +53,15 @@ def template IntExecute {{ //Write the resulting state to the execution context %(op_wb)s; - if(useCc) - { - xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); - xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); - xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; - xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; - xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); - xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); - xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; - xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; - } + return No_Fault; } }}; // Primary format for integer operate instructions: -def format IntegerOp(code, *opt_flags) {{ +def format IntOp(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) @@ -109,22 +69,3 @@ def format IntegerOp(code, *opt_flags) {{ exec_output = IntegerExecute.subst(iop) }}; -// Primary format for integer operate instructions: -def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) -}}; diff --git a/arch/mips/isa/includes.h b/arch/mips/isa/includes.isa similarity index 100% rename from arch/mips/isa/includes.h rename to arch/mips/isa/includes.isa diff --git a/arch/mips/isa/operands.def b/arch/mips/isa/operands.isa similarity index 94% rename from arch/mips/isa/operands.def rename to arch/mips/isa/operands.isa index 16d8fbceb4..58fa2d3cf5 100644 --- a/arch/mips/isa/operands.def +++ b/arch/mips/isa/operands.isa @@ -17,8 +17,8 @@ def operands {{ 'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2), 'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3), - 'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3), - 'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4), + 'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3), + 'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4), 'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1), 'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2), From 7219693f4c425b5da1557823f92da13edda6b71a Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 7 Feb 2006 19:28:19 -0500 Subject: [PATCH 7/7] Actually we do need a separate class for Integer Ops with Immediates!!! The extra class is needed because of the necessisty of an immediate member variable. Also, added some 'very modest' python code to choose between the IntOp and the IntImmOp based on the instruction name ... --HG-- extra : convert_revision : f109c12418202a99b40e270360134e8335739836 --- arch/mips/isa/formats/int.format | 57 ++++++++++++++++---------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/mips/isa/formats/int.format b/arch/mips/isa/formats/int.format index edfdddb18d..5b8df54e9d 100644 --- a/arch/mips/isa/formats/int.format +++ b/arch/mips/isa/formats/int.format @@ -12,7 +12,22 @@ output header {{ protected: /// Constructor - IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + class IntImmOp : public MipsStaticInst + { + protected: + uint16_t imm; + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) { } @@ -33,39 +48,23 @@ output decoder {{ } }}; -def template IntExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - try - { - %(op_decl)s; - %(op_rd)s; - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - // Primary format for integer operate instructions: def format IntOp(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + + //Figure out if we are creating a IntImmOp or a IntOp + strlen = len(name) + if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu')) + iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) + else: + iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) + decode_block = OperateNopCheckDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; + +