misc,python: Run pre-commit run --all-files

Applies the `pyupgrade` hook to all files in the repo.

Change-Id: I9879c634a65c5fcaa9567c63bc5977ff97d5d3bf

configs/ruby/CHI_config.py

@@ -116,7 +116,7 @@ class CHI_Node(SubSystem):
         router_list = None
 
     def __init__(self, ruby_system):
-        super(CHI_Node, self).__init__()
+        super().__init__()
         self._ruby_system = ruby_system
         self._network = ruby_system.network
 
@@ -201,7 +201,7 @@ class CHI_Cache_Controller(Cache_Controller):
     """
 
     def __init__(self, ruby_system):
-        super(CHI_Cache_Controller, self).__init__(
+        super().__init__(
             version=Versions.getVersion(Cache_Controller),
             ruby_system=ruby_system,
             mandatoryQueue=MessageBuffer(),
@@ -228,7 +228,7 @@ class CHI_L1Controller(CHI_Cache_Controller):
     """
 
     def __init__(self, ruby_system, sequencer, cache, prefetcher):
-        super(CHI_L1Controller, self).__init__(ruby_system)
+        super().__init__(ruby_system)
         self.sequencer = sequencer
         self.cache = cache
         self.use_prefetcher = False
@@ -265,7 +265,7 @@ class CHI_L2Controller(CHI_Cache_Controller):
     """
 
     def __init__(self, ruby_system, cache, prefetcher):
-        super(CHI_L2Controller, self).__init__(ruby_system)
+        super().__init__(ruby_system)
         self.sequencer = NULL
         self.cache = cache
         self.use_prefetcher = False
@@ -301,7 +301,7 @@ class CHI_HNFController(CHI_Cache_Controller):
     """
 
     def __init__(self, ruby_system, cache, prefetcher, addr_ranges):
-        super(CHI_HNFController, self).__init__(ruby_system)
+        super().__init__(ruby_system)
         self.sequencer = NULL
         self.cache = cache
         self.use_prefetcher = False
@@ -340,7 +340,7 @@ class CHI_MNController(MiscNode_Controller):
     def __init__(
         self, ruby_system, addr_range, l1d_caches, early_nonsync_comp
     ):
-        super(CHI_MNController, self).__init__(
+        super().__init__(
             version=Versions.getVersion(MiscNode_Controller),
             ruby_system=ruby_system,
             mandatoryQueue=MessageBuffer(),
@@ -371,7 +371,7 @@ class CHI_DMAController(CHI_Cache_Controller):
     """
 
     def __init__(self, ruby_system, sequencer):
-        super(CHI_DMAController, self).__init__(ruby_system)
+        super().__init__(ruby_system)
         self.sequencer = sequencer
 
         class DummyCache(RubyCache):
@@ -463,7 +463,7 @@ class CHI_RNF(CHI_Node):
         l1Iprefetcher_type=None,
         l1Dprefetcher_type=None,
     ):
-        super(CHI_RNF, self).__init__(ruby_system)
+        super().__init__(ruby_system)
 
         self._block_size_bits = int(math.log(cache_line_size, 2))
 
@@ -606,7 +606,7 @@ class CHI_HNF(CHI_Node):
     # The CHI controller can be a child of this object or another if
     # 'parent' if specified
     def __init__(self, hnf_idx, ruby_system, llcache_type, parent):
-        super(CHI_HNF, self).__init__(ruby_system)
+        super().__init__(ruby_system)
 
         addr_ranges, intlvHighBit = self.getAddrRanges(hnf_idx)
         # All ranges should have the same interleaving
@@ -644,7 +644,7 @@ class CHI_MN(CHI_Node):
     # The CHI controller can be a child of this object or another if
     # 'parent' if specified
     def __init__(self, ruby_system, l1d_caches, early_nonsync_comp=False):
-        super(CHI_MN, self).__init__(ruby_system)
+        super().__init__(ruby_system)
 
         # MiscNode has internal address range starting at 0
         addr_range = AddrRange(0, size="1kB")
@@ -675,7 +675,7 @@ class CHI_SNF_Base(CHI_Node):
     # The CHI controller can be a child of this object or another if
     # 'parent' if specified
     def __init__(self, ruby_system, parent):
-        super(CHI_SNF_Base, self).__init__(ruby_system)
+        super().__init__(ruby_system)
 
         self._cntrl = Memory_Controller(
             version=Versions.getVersion(Memory_Controller),
@@ -722,7 +722,7 @@ class CHI_SNF_BootMem(CHI_SNF_Base):
     """
 
     def __init__(self, ruby_system, parent, bootmem):
-        super(CHI_SNF_BootMem, self).__init__(ruby_system, parent)
+        super().__init__(ruby_system, parent)
         self._cntrl.memory_out_port = bootmem.port
         self._cntrl.addr_ranges = self.getMemRange(bootmem)
 
@@ -733,7 +733,7 @@ class CHI_SNF_MainMem(CHI_SNF_Base):
     """
 
     def __init__(self, ruby_system, parent, mem_ctrl=None):
-        super(CHI_SNF_MainMem, self).__init__(ruby_system, parent)
+        super().__init__(ruby_system, parent)
         if mem_ctrl:
             self._cntrl.memory_out_port = mem_ctrl.port
             self._cntrl.addr_ranges = self.getMemRange(mem_ctrl)
@@ -748,7 +748,7 @@ class CHI_RNI_Base(CHI_Node):
     # The CHI controller can be a child of this object or another if
     # 'parent' if specified
     def __init__(self, ruby_system, parent):
-        super(CHI_RNI_Base, self).__init__(ruby_system)
+        super().__init__(ruby_system)
 
         self._sequencer = RubySequencer(
             version=Versions.getSeqId(),
@@ -777,7 +777,7 @@ class CHI_RNI_DMA(CHI_RNI_Base):
     """
 
     def __init__(self, ruby_system, dma_port, parent):
-        super(CHI_RNI_DMA, self).__init__(ruby_system, parent)
+        super().__init__(ruby_system, parent)
         assert dma_port != None
         self._sequencer.in_ports = dma_port
 
@@ -788,5 +788,5 @@ class CHI_RNI_IO(CHI_RNI_Base):
     """
 
     def __init__(self, ruby_system, parent):
-        super(CHI_RNI_IO, self).__init__(ruby_system, parent)
+        super().__init__(ruby_system, parent)
         ruby_system._io_port = self._sequencer