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misc: Fix coding style for struct's opening braces

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The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-01-09 12:28:03 -03:00
committed by Daniel Carvalho
parent f96de41fcf
commit 2922f763e1
109 changed files with 584 additions and 292 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/dev/arm/flash_device.hh
View File

@@ -80,12 +80,14 @@ class FlashDevice : public AbstractNVM
};
/** Every logical address maps to a physical block and a physical page*/
struct PageMapEntry {
struct PageMapEntry
{
uint32_t page;
uint32_t block;
};
struct CallBackEntry {
struct CallBackEntry
{
Tick time;
std::function<void()> function;
};

3
src/dev/arm/fvp_base_pwr_ctrl.hh
View File

@@ -114,7 +114,8 @@ class FVPBasePwrCtrl : public BasicPioDevice
PSYSR = 0x10
};
struct Registers {
struct Registers
{
uint32_t ppoffr;
uint32_t pponr;
uint32_t pcoffr;

3
src/dev/arm/gic_v2.hh
View File

@@ -176,7 +176,8 @@ class GicV2 : public BaseGic, public BaseGicRegisters
uint32_t itLines;
/** Registers "banked for each connected processor" per ARM IHI0048B */
struct BankedRegs : public Serializable {
struct BankedRegs : public Serializable
{
/** GICD_I{S,C}ENABLER0
* interrupt enable bits for first 32 interrupts, 1b per interrupt */
uint32_t intEnabled;

51
src/dev/arm/ufs_device.hh
View File

@@ -185,7 +185,8 @@ class UFSHostDevice : public DmaDevice
* As defined in:
* http://www.jedec.org/standards-documents/results/jesd223
*/
struct HCIMem {
struct HCIMem
{
/**
* Specify the host capabilities
*/
@@ -253,7 +254,8 @@ class UFSHostDevice : public DmaDevice
* dWord1: UPIU header DW-1
* dWord2: UPIU header DW-2
*/
struct UTPUPIUHeader {
struct UTPUPIUHeader
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t dWord2;
@@ -267,7 +269,8 @@ class UFSHostDevice : public DmaDevice
* senseDataLen: Sense data length DW-8 U16
* senseData: Sense data field DW-8 to DW-12
*/
struct UTPUPIURSP {
struct UTPUPIURSP
{
struct UTPUPIUHeader header;
uint32_t residualTransferCount;
uint32_t reserved[4];
@@ -283,7 +286,8 @@ class UFSHostDevice : public DmaDevice
* inputParam3: Input param 3 DW-5
* reserved: Reserver DW-6 to DW-7
*/
struct UTPUPIUTaskReq {
struct UTPUPIUTaskReq
{
struct UTPUPIUHeader header;
uint32_t inputParam1;
uint32_t inputParam2;
@@ -298,7 +302,8 @@ class UFSHostDevice : public DmaDevice
* reserved: Reserved for future use DW-2
* size: size of physical segment DW-3
*/
struct UFSHCDSGEntry {
struct UFSHCDSGEntry
{
uint32_t baseAddr;
uint32_t upperAddr;
uint32_t reserved;
@@ -312,7 +317,8 @@ class UFSHostDevice : public DmaDevice
* PRDTable: Physcial Region Descriptor
* All lengths as defined by JEDEC220
*/
struct UTPTransferCMDDesc {
struct UTPTransferCMDDesc
{
uint8_t commandUPIU[128];
uint8_t responseUPIU[128];
struct UFSHCDSGEntry PRDTable[128];
@@ -321,7 +327,8 @@ class UFSHostDevice : public DmaDevice
/**
* UPIU tranfer message.
*/
struct UPIUMessage {
struct UPIUMessage
{
struct UTPUPIUHeader header;
uint32_t dataOffset;
uint32_t dataCount;
@@ -338,7 +345,8 @@ class UFSHostDevice : public DmaDevice
* PRDTableLength: Physical region descriptor length DW-7
* PRDTableOffset: Physical region descriptor offset DW-7
*/
struct UTPTransferReqDesc {
struct UTPTransferReqDesc
{
/**
* struct RequestDescHeader
@@ -347,7 +355,8 @@ class UFSHostDevice : public DmaDevice
* dword2: Descriptor Header DW2
* dword3: Descriptor Header DW3
*/
struct RequestDescHeader {
struct RequestDescHeader
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t dWord2;
@@ -371,7 +380,8 @@ class UFSHostDevice : public DmaDevice
* SCSI reply structure. In here is all the information that is needed to
* build a SCSI reply.
*/
struct SCSIReply {
struct SCSIReply
{
void reset() {
memset(static_cast<void*>(this), 0, sizeof(*this));
}
@@ -391,7 +401,8 @@ class UFSHostDevice : public DmaDevice
* This structure is defined in the SCSI standard, and can also be found in
* the UFS standard. http://www.jedec.org/standards-documents/results/jesd220
*/
struct LUNInfo {
struct LUNInfo
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t vendor0;
@@ -422,7 +433,8 @@ class UFSHostDevice : public DmaDevice
* @filePointer this does not point to a file, but to a position on the disk
* image (which is from the software systems perspective a position in a file)
*/
struct transferInfo {
struct transferInfo
{
std::vector <uint8_t> buffer;
uint32_t size;
uint64_t offset;
@@ -434,7 +446,8 @@ class UFSHostDevice : public DmaDevice
* transfer completion info.
* This information is needed by transferDone to finish the transfer.
*/
struct transferDoneInfo {
struct transferDoneInfo
{
Addr responseStartAddr;
uint32_t reqPos;
struct UTPUPIURSP requestOut;
@@ -448,7 +461,8 @@ class UFSHostDevice : public DmaDevice
/**
* Transfer start information.
*/
struct transferStart {
struct transferStart
{
struct UTPTransferReqDesc* destination;
uint32_t mask;
Addr address;
@@ -460,7 +474,8 @@ class UFSHostDevice : public DmaDevice
/**
* Task start information. This is for the device, so no lun id needed.
*/
struct taskStart {
struct taskStart
{
struct UTPUPIUTaskReq destination;
uint32_t mask;
Addr address;
@@ -472,7 +487,8 @@ class UFSHostDevice : public DmaDevice
* After a SCSI command has been identified, the SCSI resume function will
* handle it. This information will provide context information.
*/
struct SCSIResumeInfo {
struct SCSIResumeInfo
{
struct UTPTransferReqDesc* RequestIn;
int reqPos;
Addr finalAddress;
@@ -485,7 +501,8 @@ class UFSHostDevice : public DmaDevice
* Disk transfer burst information. Needed to allow communication between the
* disk transactions and dma transactions.
*/
struct writeToDiskBurst {
struct writeToDiskBurst
{
Addr start;
uint64_t SCSIDiskOffset;
uint32_t size;

3
src/dev/arm/vgic.hh
View File

@@ -152,7 +152,8 @@ class VGic : public PioDevice
/* State per CPU. EVERYTHING should be in this struct and simply replicated
* N times.
*/
struct vcpuIntData : public Serializable {
struct vcpuIntData : public Serializable
{
vcpuIntData()
: vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),

3
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -371,7 +371,8 @@ class HSAPacketProcessor: public DmaDevice
/**
* Calls getCurrentEntry once the queueEntry has been dmaRead.
*/
struct dma_series_ctx {
struct dma_series_ctx
{
// deal with the fact dma ops can complete out of issue order
uint32_t pkts_ttl;
uint32_t pkts_2_go;

111
src/dev/hsa/kfd_ioctl.h
View File

@@ -29,7 +29,8 @@
#define KFD_IOCTL_MAJOR_VERSION 1
#define KFD_IOCTL_MINOR_VERSION 2
struct kfd_ioctl_get_version_args {
struct kfd_ioctl_get_version_args
{
uint32_t major_version; /* from KFD */
uint32_t minor_version; /* from KFD */
};
@@ -42,7 +43,8 @@ struct kfd_ioctl_get_version_args {
#define KFD_MAX_QUEUE_PERCENTAGE 100
#define KFD_MAX_QUEUE_PRIORITY 15
struct kfd_ioctl_create_queue_args {
struct kfd_ioctl_create_queue_args
{
uint64_t ring_base_address; /* to KFD */
uint64_t write_pointer_address; /* from KFD */
uint64_t read_pointer_address; /* from KFD */
@@ -62,12 +64,14 @@ struct kfd_ioctl_create_queue_args {
uint32_t ctl_stack_size; /* to KFD */
};
struct kfd_ioctl_destroy_queue_args {
struct kfd_ioctl_destroy_queue_args
{
uint32_t queue_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_update_queue_args {
struct kfd_ioctl_update_queue_args
{
uint64_t ring_base_address; /* to KFD */
uint32_t queue_id; /* to KFD */
@@ -76,7 +80,8 @@ struct kfd_ioctl_update_queue_args {
uint32_t queue_priority; /* to KFD */
};
struct kfd_ioctl_set_cu_mask_args {
struct kfd_ioctl_set_cu_mask_args
{
uint32_t queue_id; /* to KFD */
uint32_t num_cu_mask; /* to KFD */
uint64_t cu_mask_ptr; /* to KFD */
@@ -86,7 +91,8 @@ struct kfd_ioctl_set_cu_mask_args {
#define KFD_IOC_CACHE_POLICY_COHERENT 0
#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
struct kfd_ioctl_set_memory_policy_args {
struct kfd_ioctl_set_memory_policy_args
{
uint64_t alternate_aperture_base; /* to KFD */
uint64_t alternate_aperture_size; /* to KFD */
@@ -96,7 +102,8 @@ struct kfd_ioctl_set_memory_policy_args {
uint32_t pad;
};
struct kfd_ioctl_set_trap_handler_args {
struct kfd_ioctl_set_trap_handler_args
{
uint64_t tba_addr;
uint64_t tma_addr;
uint32_t gpu_id; /* to KFD */
@@ -110,7 +117,8 @@ struct kfd_ioctl_set_trap_handler_args {
* In case of GPU reset, the counter should not be affected.
*/
struct kfd_ioctl_get_clock_counters_args {
struct kfd_ioctl_get_clock_counters_args
{
uint64_t gpu_clock_counter; /* from KFD */
uint64_t cpu_clock_counter; /* from KFD */
uint64_t system_clock_counter; /* from KFD */
@@ -122,7 +130,8 @@ struct kfd_ioctl_get_clock_counters_args {
#define NUM_OF_SUPPORTED_GPUS 7
struct kfd_process_device_apertures {
struct kfd_process_device_apertures
{
uint64_t lds_base; /* from KFD */
uint64_t lds_limit; /* from KFD */
uint64_t scratch_base; /* from KFD */
@@ -137,7 +146,8 @@ struct kfd_process_device_apertures {
* kfd_ioctl_get_process_apertures_new instead, which supports
* arbitrary numbers of GPUs.
*/
struct kfd_ioctl_get_process_apertures_args {
struct kfd_ioctl_get_process_apertures_args
{
struct kfd_process_device_apertures
process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
@@ -146,7 +156,8 @@ struct kfd_ioctl_get_process_apertures_args {
uint32_t pad;
};
struct kfd_ioctl_get_process_apertures_new_args {
struct kfd_ioctl_get_process_apertures_new_args
{
/* User allocated. Pointer to struct kfd_process_device_apertures
* filled in by Kernel
*/
@@ -163,23 +174,27 @@ struct kfd_ioctl_get_process_apertures_new_args {
#define MAX_ALLOWED_AW_BUFF_SIZE 4096
#define MAX_ALLOWED_WAC_BUFF_SIZE 128
struct kfd_ioctl_dbg_register_args {
struct kfd_ioctl_dbg_register_args
{
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_dbg_unregister_args {
struct kfd_ioctl_dbg_unregister_args
{
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_dbg_address_watch_args {
struct kfd_ioctl_dbg_address_watch_args
{
uint64_t content_ptr; /* a pointer to the actual content */
uint32_t gpu_id; /* to KFD */
uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
};
struct kfd_ioctl_dbg_wave_control_args {
struct kfd_ioctl_dbg_wave_control_args
{
uint64_t content_ptr; /* a pointer to the actual content */
uint32_t gpu_id; /* to KFD */
uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
@@ -209,7 +224,8 @@ struct kfd_ioctl_dbg_wave_control_args {
*/
#define KFD_SIGNAL_EVENT_LIMIT (4096 + 512)
struct kfd_ioctl_create_event_args {
struct kfd_ioctl_create_event_args
{
uint64_t event_page_offset; /* from KFD */
uint32_t event_trigger_data; /* from KFD - signal events only */
uint32_t event_type; /* to KFD */
@@ -220,22 +236,26 @@ struct kfd_ioctl_create_event_args {
uint32_t event_slot_index; /* from KFD */
};
struct kfd_ioctl_destroy_event_args {
struct kfd_ioctl_destroy_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_set_event_args {
struct kfd_ioctl_set_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_reset_event_args {
struct kfd_ioctl_reset_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_memory_exception_failure {
struct kfd_memory_exception_failure
{
uint32_t NotPresent; /* Page not present or supervisor privilege */
uint32_t ReadOnly; /* Write access to a read-only page */
uint32_t NoExecute; /* Execute access to a page marked NX */
@@ -243,7 +263,8 @@ struct kfd_memory_exception_failure {
};
/* memory exception data */
struct kfd_hsa_memory_exception_data {
struct kfd_hsa_memory_exception_data
{
struct kfd_memory_exception_failure failure;
uint64_t va;
uint32_t gpu_id;
@@ -251,7 +272,8 @@ struct kfd_hsa_memory_exception_data {
};
/* Event data */
struct kfd_event_data {
struct kfd_event_data
{
union {
struct kfd_hsa_memory_exception_data memory_exception_data;
}; /* From KFD */
@@ -261,7 +283,8 @@ struct kfd_event_data {
uint32_t pad;
};
struct kfd_ioctl_wait_events_args {
struct kfd_ioctl_wait_events_args
{
uint64_t events_ptr; /* pointed to struct
kfd_event_data array, to KFD */
uint32_t num_events; /* to KFD */
@@ -270,7 +293,8 @@ struct kfd_ioctl_wait_events_args {
uint32_t wait_result; /* from KFD */
};
struct kfd_ioctl_alloc_memory_of_scratch_args {
struct kfd_ioctl_alloc_memory_of_scratch_args
{
uint64_t va_addr; /* to KFD */
uint64_t size; /* to KFD */
uint32_t gpu_id; /* to KFD */
@@ -291,7 +315,8 @@ struct kfd_ioctl_alloc_memory_of_scratch_args {
#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTE_ACCESS (1 << 26)
#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 25)
struct kfd_ioctl_alloc_memory_of_gpu_args {
struct kfd_ioctl_alloc_memory_of_gpu_args
{
uint64_t va_addr; /* to KFD */
uint64_t size; /* to KFD */
uint64_t handle; /* from KFD */
@@ -300,18 +325,21 @@ struct kfd_ioctl_alloc_memory_of_gpu_args {
uint32_t flags;
};
struct kfd_ioctl_free_memory_of_gpu_args {
struct kfd_ioctl_free_memory_of_gpu_args
{
uint64_t handle; /* to KFD */
};
struct kfd_ioctl_map_memory_to_gpu_args {
struct kfd_ioctl_map_memory_to_gpu_args
{
uint64_t handle; /* to KFD */
uint64_t device_ids_array_ptr; /* to KFD */
uint32_t device_ids_array_size; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_unmap_memory_from_gpu_args {
struct kfd_ioctl_unmap_memory_from_gpu_args
{
uint64_t handle; /* to KFD */
uint64_t device_ids_array_ptr; /* to KFD */
uint32_t device_ids_array_size; /* to KFD */
@@ -323,7 +351,8 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
* has been superseded by the pair of get_dmabuf_info and
* import_dmabuf, which is implemented for all supported GPUs.
*/
struct kfd_ioctl_open_graphic_handle_args {
struct kfd_ioctl_open_graphic_handle_args
{
uint64_t va_addr; /* to KFD */
uint64_t handle; /* from KFD */
uint32_t gpu_id; /* to KFD */
@@ -332,14 +361,16 @@ struct kfd_ioctl_open_graphic_handle_args {
uint32_t pad;
};
struct kfd_ioctl_set_process_dgpu_aperture_args {
struct kfd_ioctl_set_process_dgpu_aperture_args
{
uint64_t dgpu_base;
uint64_t dgpu_limit;
uint32_t gpu_id;
uint32_t pad;
};
struct kfd_ioctl_get_dmabuf_info_args {
struct kfd_ioctl_get_dmabuf_info_args
{
uint64_t size; /* from KFD */
uint64_t metadata_ptr; /* to KFD */
uint32_t metadata_size; /* to KFD (space allocated by user)
@@ -349,21 +380,24 @@ struct kfd_ioctl_get_dmabuf_info_args {
uint32_t dmabuf_fd; /* to KFD */
};
struct kfd_ioctl_import_dmabuf_args {
struct kfd_ioctl_import_dmabuf_args
{
uint64_t va_addr; /* to KFD */
uint64_t handle; /* from KFD */
uint32_t gpu_id; /* to KFD */
uint32_t dmabuf_fd; /* to KFD */
};
struct kfd_ioctl_ipc_export_handle_args {
struct kfd_ioctl_ipc_export_handle_args
{
uint64_t handle; /* to KFD */
uint32_t share_handle[4]; /* from KFD */
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_ipc_import_handle_args {
struct kfd_ioctl_ipc_import_handle_args
{
uint64_t handle; /* from KFD */
uint64_t va_addr; /* to KFD */
uint64_t mmap_offset; /* from KFD */
@@ -372,7 +406,8 @@ struct kfd_ioctl_ipc_import_handle_args {
uint32_t pad;
};
struct kfd_ioctl_get_tile_config_args {
struct kfd_ioctl_get_tile_config_args
{
/* to KFD: pointer to tile array */
uint64_t tile_config_ptr;
/* to KFD: pointer to macro tile array */
@@ -395,7 +430,8 @@ struct kfd_ioctl_get_tile_config_args {
*/
};
struct kfd_memory_range {
struct kfd_memory_range
{
uint64_t va_addr;
uint64_t size;
};
@@ -409,7 +445,8 @@ struct kfd_memory_range {
#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT)
#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT)
struct kfd_ioctl_cross_memory_copy_args {
struct kfd_ioctl_cross_memory_copy_args
{
/* to KFD: Process ID of the remote process */
uint32_t pid;
/* to KFD: See above definition */

6
src/dev/net/etherdump.cc
View File

@@ -53,7 +53,8 @@ EtherDump::EtherDump(const Params &p)
#define PCAP_VERSION_MAJOR 2
#define PCAP_VERSION_MINOR 4
struct pcap_file_header {
struct pcap_file_header
{
uint32_t magic;
uint16_t version_major;
uint16_t version_minor;
@@ -63,7 +64,8 @@ struct pcap_file_header {
uint32_t linktype; // data link type (DLT_*)
};
struct pcap_pkthdr {
struct pcap_pkthdr
{
uint32_t seconds;
uint32_t microseconds;
uint32_t caplen; // length of portion present

6
src/dev/net/etherswitch.hh
View File

@@ -117,7 +117,8 @@ class EtherSwitch : public SimObject
class PortFifo : public Serializable
{
protected:
struct EntryOrder {
struct EntryOrder
{
bool operator() (const PortFifoEntry& lhs,
const PortFifoEntry& rhs) const
{
@@ -171,7 +172,8 @@ class EtherSwitch : public SimObject
EventFunctionWrapper txEvent;
};
struct SwitchTableEntry {
struct SwitchTableEntry
{
Interface *interface;
Tick lastUseTime;
};

12
src/dev/net/i8254xGBe_defs.hh
View File

@@ -186,7 +186,8 @@ enum IntTypes
};
// Receive Descriptor struct
struct RxDesc {
struct RxDesc
{
union {
struct {
Addr buf;
@@ -221,7 +222,8 @@ struct RxDesc {
};
};
struct TxDesc {
struct TxDesc
{
uint64_t d1;
uint64_t d2;
};
@@ -294,9 +296,11 @@ inline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); }
inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
struct Regs : public Serializable {
struct Regs : public Serializable
{
template<class T>
struct Reg {
struct Reg
{
T _data;
T operator()() { return _data; }
const Reg<T> &operator=(T d) { _data = d; return *this;}

6
src/dev/net/ns_gige.hh
View File

@@ -58,7 +58,8 @@ const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
/**
* Ethernet device registers
*/
struct dp_regs {
struct dp_regs
{
uint32_t command;
uint32_t config;
uint32_t mear;
@@ -95,7 +96,8 @@ struct dp_regs {
uint32_t tesr;
};
struct dp_rom {
struct dp_rom
{
/**
* for perfect match memory.
* the linux driver doesn't use any other ROM

6
src/dev/net/ns_gige_reg.h
View File

@@ -351,14 +351,16 @@ enum M5ControlRegister {
M5REG_TX_THREAD = 0x00000001
};
struct ns_desc32 {
struct ns_desc32
{
uint32_t link; /* link field to next descriptor in linked list */
uint32_t bufptr; /* pointer to the first fragment or buffer */
uint32_t cmdsts; /* command/status field */
uint32_t extsts; /* extended status field for VLAN and IP info */
};
struct ns_desc64 {
struct ns_desc64
{
uint64_t link; /* link field to next descriptor in linked list */
uint64_t bufptr; /* pointer to the first fragment or buffer */
uint32_t cmdsts; /* command/status field */

3
src/dev/net/sinic.hh
View File

@@ -129,7 +129,8 @@ class Device : public Base
uint64_t RxStatus; // 0x78
} regs;
struct VirtualReg {
struct VirtualReg
{
uint64_t RxData;
uint64_t RxDone;
uint64_t TxData;

12
src/dev/pci/copy_engine_defs.hh
View File

@@ -62,7 +62,8 @@ const uint32_t DESC_CTRL_CP_STS = 0x00000008;
const uint32_t DESC_CTRL_FRAME = 0x00000010;
const uint32_t DESC_CTRL_NULL = 0x00000020;
struct DmaDesc {
struct DmaDesc
{
uint32_t len;
uint32_t command;
Addr src;
@@ -91,7 +92,8 @@ struct DmaDesc {
inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
template<class T>
struct Reg {
struct Reg
{
T _data;
T operator()() { return _data; }
const Reg<T> &operator=(T d) { _data = d; return *this;}
@@ -109,7 +111,8 @@ struct Reg {
};
struct Regs : public Serializable {
struct Regs : public Serializable
{
uint8_t chanCount;
uint8_t xferCap;
@@ -141,7 +144,8 @@ struct Regs : public Serializable {
};
struct ChanRegs : public Serializable {
struct ChanRegs : public Serializable
{
struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00
using Reg<uint16_t>::operator =;
ADD_FIELD16(interrupt_disable,0,1);

6
src/dev/pci/pcireg.h
View File

@@ -307,7 +307,8 @@ union MSIXTable {
};
#define MSIXVECS_PER_PBA 64
struct MSIXPbaEntry {
struct MSIXPbaEntry
{
uint64_t bits;
};
@@ -315,7 +316,8 @@ struct MSIXPbaEntry {
* Defines the PCI Express capability register and its associated bitfields
* for a PCIe device.
*/
struct PXCAP {
struct PXCAP
{
uint8_t data[48];
struct {
uint16_t pxid; /* 0:7 cid

3
src/dev/riscv/plic.hh
View File

@@ -86,7 +86,8 @@ using namespace RiscvISA;
* writing to M mode registers)
*/
struct PlicOutput {
struct PlicOutput
{
std::vector<uint32_t> maxID;
std::vector<uint32_t> maxPriority;
};

9
src/dev/sparc/iob.hh
View File

@@ -86,17 +86,20 @@ class Iob : public PioDevice
NumDeviceIds
};
struct IntMan {
struct IntMan
{
int cpu;
int vector;
};
struct IntCtl {
struct IntCtl
{
bool mask;
bool pend;
};
struct IntBusy {
struct IntBusy
{
bool busy;
int source;
};

3
src/dev/storage/disk_image.hh
View File

@@ -108,7 +108,8 @@ class CowDiskImage : public DiskImage
static const uint32_t VersionMinor;
protected:
struct Sector {
struct Sector
{
uint8_t data[SectorSize];
};
typedef std::unordered_map<uint64_t, Sector *> SectorTable;

3
src/dev/storage/ide_atareg.h
View File

@@ -64,7 +64,8 @@
* ATA_* : ATA only
* ATAPI_* : ATAPI only.
*/
struct ataparams {
struct ataparams
{
/* drive info */
uint16_t atap_config; /* 0: general configuration */
#define WDC_CFG_ATAPI_MASK 0xc000

3
src/dev/virtio/base.hh
View File

@@ -464,7 +464,8 @@ class VirtQueue : public Serializable
typedef uint16_t Flags;
typedef uint16_t Index;
struct M5_ATTR_PACKED Header {
struct M5_ATTR_PACKED Header
{
Flags flags;
Index index;
};

6
src/dev/virtio/block.hh
View File

@@ -81,7 +81,8 @@ class VirtIOBlock : public VirtIODeviceBase
* @note This needs to be changed if the supported feature set
* changes!
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint64_t capacity;
};
Config config;
@@ -122,7 +123,8 @@ class VirtIOBlock : public VirtIODeviceBase
/** @} */
/** VirtIO block device request as sent by guest */
struct M5_ATTR_PACKED BlkRequest {
struct M5_ATTR_PACKED BlkRequest
{
RequestType type;
uint32_t reserved;
uint64_t sector;

3
src/dev/virtio/console.hh
View File

@@ -77,7 +77,8 @@ class VirtIOConsole : public VirtIODeviceBase
* @note This needs to be changed if the multiport feature is
* announced!
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint16_t cols;
uint16_t rows;
};

3
src/dev/virtio/fs9p.cc
View File

@@ -60,7 +60,8 @@
#include "params/VirtIO9PSocket.hh"
#include "sim/system.hh"
struct P9MsgInfo {
struct P9MsgInfo
{
P9MsgInfo(P9MsgType _type, std::string _name)
: type(_type), name(_name) {}

6
src/dev/virtio/fs9p.hh
View File

@@ -50,7 +50,8 @@ struct VirtIO9PBaseParams;
typedef uint8_t P9MsgType;
typedef uint16_t P9Tag;
struct M5_ATTR_PACKED P9MsgHeader {
struct M5_ATTR_PACKED P9MsgHeader
{
/** Length including header */
uint32_t len;
/** Message type */
@@ -120,7 +121,8 @@ class VirtIO9PBase : public VirtIODeviceBase
* @note The fields in this structure depend on the features
* exposed to the guest.
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint16_t len;
char tag[];
};

15
src/dev/virtio/virtio_ring.h
View File

@@ -59,7 +59,8 @@
#define VIRTIO_RING_F_EVENT_IDX 29
/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
struct vring_desc {
struct vring_desc
{
/* Address (guest-physical). */
uint64_t addr;
/* Length. */
@@ -70,27 +71,31 @@ struct vring_desc {
uint16_t next;
};
struct vring_avail {
struct vring_avail
{
uint16_t flags;
uint16_t idx;
uint16_t ring[];
};
/* u32 is used here for ids for padding reasons. */
struct vring_used_elem {
struct vring_used_elem
{
/* Index of start of used descriptor chain. */
uint32_t id;
/* Total length of the descriptor chain which was used (written to) */
uint32_t len;
};
struct vring_used {
struct vring_used
{
uint16_t flags;
uint16_t idx;
struct vring_used_elem ring[];
};
struct vring {
struct vring
{
unsigned int num;
struct vring_desc *desc;