misc: Fix coding style for struct's opening braces

The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/base.hh

@@ -146,7 +146,8 @@ class BaseCPU : public ClockedObject
     const unsigned int _cacheLineSize;
 
     /** Global CPU statistics that are merged into the Root object. */
-    struct GlobalStats : public Stats::Group {
+    struct GlobalStats : public Stats::Group
+    {
         GlobalStats(::Stats::Group *parent);
 
         ::Stats::Value simInsts;

src/cpu/kvm/base.hh

@@ -780,7 +780,8 @@ class BaseKvmCPU : public BaseCPU
 
   public:
     /* @{ */
-    struct StatGroup : public Stats::Group {
+    struct StatGroup : public Stats::Group
+    {
         StatGroup(Stats::Group *parent);
         Stats::Scalar committedInsts;
         Stats::Scalar numVMExits;

src/cpu/kvm/device.cc

@@ -60,7 +60,8 @@ void
 KvmDevice::getAttrPtr(uint32_t group, uint64_t attr, void *data) const
 {
 #ifdef KVM_GET_DEVICE_ATTR
-  struct kvm_device_attr dattr = {
+    struct kvm_device_attr dattr =
+    {
         0, // Flags
         group,
         attr,
@@ -80,7 +81,8 @@ void
 KvmDevice::setAttrPtr(uint32_t group, uint64_t attr, const void *data) const
 {
 #ifdef KVM_SET_DEVICE_ATTR
-    struct kvm_device_attr dattr = {
+    struct kvm_device_attr dattr =
+    {
         0, // Flags
         group,
         attr,
@@ -100,7 +102,8 @@ bool
 KvmDevice::hasAttr(uint32_t group, uint64_t attr) const
 {
 #ifdef KVM_HAS_DEVICE_ATTR
-    struct kvm_device_attr dattr = {
+    struct kvm_device_attr dattr =
+    {
         0, // Flags
         group,
         attr,

src/cpu/minor/decode.hh

@@ -88,7 +88,8 @@ class Decode : public Named
   protected:
     /** Data members after this line are cycle-to-cycle state */
 
-    struct DecodeThreadInfo {
+    struct DecodeThreadInfo
+    {
 
         /** Default Constructor */
         DecodeThreadInfo() :

src/cpu/minor/execute.hh

@@ -145,7 +145,8 @@ class Execute : public Named
         DrainAllInsts /* Discarding all remaining insts */
     };
 
-    struct ExecuteThreadInfo {
+    struct ExecuteThreadInfo
+    {
         /** Constructor */
         ExecuteThreadInfo(unsigned int insts_committed) :
             inputIndex(0),

src/cpu/minor/fetch1.hh

@@ -236,7 +236,8 @@ class Fetch1 : public Named
 
     /** Stage cycle-by-cycle state */
 
-    struct Fetch1ThreadInfo {
+    struct Fetch1ThreadInfo
+    {
 
         /** Consturctor to initialize all fields. */
         Fetch1ThreadInfo() :

src/cpu/minor/fetch2.hh

@@ -98,7 +98,8 @@ class Fetch2 : public Named
   protected:
     /** Data members after this line are cycle-to-cycle state */
 
-    struct Fetch2ThreadInfo {
+    struct Fetch2ThreadInfo
+    {
 
         /** Default constructor */
         Fetch2ThreadInfo() :

src/cpu/o3/comm.hh

@@ -51,7 +51,8 @@
 
 /** Struct that defines the information passed from fetch to decode. */
 template<class Impl>
-struct DefaultFetchDefaultDecode {
+struct DefaultFetchDefaultDecode
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     int size;
@@ -64,7 +65,8 @@ struct DefaultFetchDefaultDecode {
 
 /** Struct that defines the information passed from decode to rename. */
 template<class Impl>
-struct DefaultDecodeDefaultRename {
+struct DefaultDecodeDefaultRename
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     int size;
@@ -74,7 +76,8 @@ struct DefaultDecodeDefaultRename {
 
 /** Struct that defines the information passed from rename to IEW. */
 template<class Impl>
-struct DefaultRenameDefaultIEW {
+struct DefaultRenameDefaultIEW
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     int size;
@@ -84,7 +87,8 @@ struct DefaultRenameDefaultIEW {
 
 /** Struct that defines the information passed from IEW to commit. */
 template<class Impl>
-struct DefaultIEWDefaultCommit {
+struct DefaultIEWDefaultCommit
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     int size;
@@ -102,7 +106,8 @@ struct DefaultIEWDefaultCommit {
 };
 
 template<class Impl>
-struct IssueStruct {
+struct IssueStruct
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     int size;
@@ -112,9 +117,11 @@ struct IssueStruct {
 
 /** Struct that defines all backwards communication. */
 template<class Impl>
-struct TimeBufStruct {
+struct TimeBufStruct
+{
     typedef typename Impl::DynInstPtr DynInstPtr;
-    struct decodeComm {
+    struct decodeComm
+    {
         TheISA::PCState nextPC;
         DynInstPtr mispredictInst;
         DynInstPtr squashInst;
@@ -130,12 +137,14 @@ struct TimeBufStruct {
 
     decodeComm decodeInfo[Impl::MaxThreads];
 
-    struct renameComm {
+    struct renameComm
+    {
     };
 
     renameComm renameInfo[Impl::MaxThreads];
 
-    struct iewComm {
+    struct iewComm
+    {
         // Also eventually include skid buffer space.
         unsigned freeIQEntries;
         unsigned freeLQEntries;
@@ -153,7 +162,8 @@ struct TimeBufStruct {
 
     iewComm iewInfo[Impl::MaxThreads];
 
-    struct commitComm {
+    struct commitComm
+    {
         /////////////////////////////////////////////////////////////////////
         // This code has been re-structured for better packing of variables
         // instead of by stage which is the more logical way to arrange the

src/cpu/o3/commit.hh

@@ -480,7 +480,8 @@ class DefaultCommit
     int htmStarts[Impl::MaxThreads];
     int htmStops[Impl::MaxThreads];
 
-    struct CommitStats : public Stats::Group {
+    struct CommitStats : public Stats::Group
+    {
         CommitStats(O3CPU *cpu, DefaultCommit *commit);
         /** Stat for the total number of squashed instructions discarded by
          * commit.

src/cpu/o3/decode.hh

@@ -246,7 +246,8 @@ class DefaultDecode
     bool wroteToTimeBuffer;
 
     /** Source of possible stalls. */
-    struct Stalls {
+    struct Stalls
+    {
         bool rename;
     };
 
@@ -292,7 +293,8 @@ class DefaultDecode
      */
     bool squashAfterDelaySlot[Impl::MaxThreads];
 
-    struct DecodeStats : public Stats::Group {
+    struct DecodeStats : public Stats::Group
+    {
         DecodeStats(O3CPU *cpu);
 
         /** Stat for total number of idle cycles. */

src/cpu/o3/fetch.hh

@@ -449,7 +449,8 @@ class DefaultFetch
     int numInst;
 
     /** Source of possible stalls. */
-    struct Stalls {
+    struct Stalls
+    {
         bool decode;
         bool drain;
     };

src/cpu/o3/inst_queue.hh

@@ -332,7 +332,8 @@ class InstructionQueue
      * numbers (and hence are older) will be at the top of the
      * priority queue.
      */
-    struct pqCompare {
+    struct pqCompare
+    {
         bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
         {
             return lhs->seqNum > rhs->seqNum;
@@ -359,7 +360,8 @@ class InstructionQueue
     typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
 
     /** Entry for the list age ordering by op class. */
-    struct ListOrderEntry {
+    struct ListOrderEntry
+    {
         OpClass queueType;
         InstSeqNum oldestInst;
     };

src/cpu/o3/mem_dep_unit.hh

@@ -51,7 +51,8 @@
 #include "cpu/inst_seq.hh"
 #include "debug/MemDepUnit.hh"
 
-struct SNHash {
+struct SNHash
+{
     size_t operator() (const InstSeqNum &seq_num) const {
         unsigned a = (unsigned)seq_num;
         unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;

src/cpu/o3/probe/elastic_trace.hh

@@ -504,7 +504,8 @@ class ElasticTrace : public ProbeListenerObject
      */
     bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
 
-    struct ElasticTraceStats : public Stats::Group {
+    struct ElasticTraceStats : public Stats::Group
+    {
         ElasticTraceStats(Stats::Group *parent);
 
         /** Number of register dependencies recorded during tracing */

src/cpu/o3/rename.hh

@@ -295,7 +295,8 @@ class DefaultRename
      * the instruction's sequence number, the arch register, the old physical
      * register for that arch. register, and the new physical register.
      */
-    struct RenameHistory {
+    struct RenameHistory
+    {
         RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
                       PhysRegIdPtr _newPhysReg,
                       PhysRegIdPtr _prevPhysReg)
@@ -388,7 +389,8 @@ class DefaultRename
     /** Structures whose free entries impact the amount of instructions that
      * can be renamed.
      */
-    struct FreeEntries {
+    struct FreeEntries
+    {
         unsigned iqEntries;
         unsigned robEntries;
         unsigned lqEntries;
@@ -407,7 +409,8 @@ class DefaultRename
     bool emptyROB[Impl::MaxThreads];
 
     /** Source of possible stalls. */
-    struct Stalls {
+    struct Stalls
+    {
         bool iew;
         bool commit;
     };
@@ -478,7 +481,8 @@ class DefaultRename
      */
     inline void incrFullStat(const FullSource &source);
 
-    struct RenameStats : public Stats::Group {
+    struct RenameStats : public Stats::Group
+    {
         RenameStats(Stats::Group *parent);
 
         /** Stat for total number of cycles spent squashing. */

src/cpu/o3/rob.hh

@@ -321,7 +321,8 @@ class ROB
     ThreadID numThreads;
 
 
-    struct ROBStats : public Stats::Group {
+    struct ROBStats : public Stats::Group
+    {
         ROBStats(Stats::Group *parent);
 
         // The number of rob_reads

src/cpu/o3/store_set.hh

@@ -37,7 +37,8 @@
 #include "base/types.hh"
 #include "cpu/inst_seq.hh"
 
-struct ltseqnum {
+struct ltseqnum
+{
     bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
     {
         return lhs > rhs;

src/cpu/o3/thread_state.hh

@@ -61,7 +61,8 @@ class Process;
  * thread's process, such as syscalls and checking valid addresses.
  */
 template <class Impl>
-struct O3ThreadState : public ThreadState {
+struct O3ThreadState : public ThreadState
+{
     typedef ThreadContext::Status Status;
     typedef typename Impl::O3CPU O3CPU;
 

src/cpu/pred/bi_mode.hh

@@ -65,7 +65,8 @@ class BiModeBP : public BPredUnit
   private:
     void updateGlobalHistReg(ThreadID tid, bool taken);
 
-    struct BPHistory {
+    struct BPHistory
+    {
         unsigned globalHistoryReg;
         // was the taken array's prediction used?
         // true: takenPred used

src/cpu/pred/bpred_unit.hh

@@ -185,7 +185,8 @@ class BPredUnit : public SimObject
     void dump();
 
   private:
-    struct PredictorHistory {
+    struct PredictorHistory
+    {
         /**
          * Makes a predictor history struct that contains any
          * information needed to update the predictor, BTB, and RAS.
@@ -277,7 +278,8 @@ class BPredUnit : public SimObject
     /** The indirect target predictor. */
     IndirectPredictor * iPred;
 
-    struct BPredUnitStats : public Stats::Group {
+    struct BPredUnitStats : public Stats::Group
+    {
         BPredUnitStats(Stats::Group *parent);
 
         /** Stat for number of BP lookups. */

src/cpu/pred/loop_predictor.hh

@@ -83,7 +83,8 @@ class LoopPredictor : public SimObject
     const unsigned initialLoopAge;
     const bool optionalAgeReset;
 
-    struct LoopPredictorStats : public Stats::Group {
+    struct LoopPredictorStats : public Stats::Group
+    {
         LoopPredictorStats(Stats::Group *parent);
         Stats::Scalar correct;
         Stats::Scalar wrong;

src/cpu/pred/multiperspective_perceptron.cc

@@ -249,7 +249,8 @@ MultiperspectivePerceptron::findBest(ThreadID tid,
     if (threshold < 0) {
         return;
     }
-    struct BestPair {
+    struct BestPair
+    {
         int index;
         int mpreds;
         bool operator<(BestPair const &bp) const

src/cpu/pred/multiperspective_perceptron.hh

@@ -141,7 +141,8 @@ class MultiperspectivePerceptron : public BPredUnit
     /**
      * Entry of the branch filter
      */
-    struct FilterEntry {
+    struct FilterEntry
+    {
         /** Has this branch been taken at least once? */
         bool seenTaken;
         /** Has this branch been not taken at least once? */
@@ -215,7 +216,8 @@ class MultiperspectivePerceptron : public BPredUnit
     /**
      * Base class to implement the predictor tables.
      */
-    struct HistorySpec {
+    struct HistorySpec
+    {
         /** First parameter */
         const int p1;
         /** Second parameter */
@@ -287,7 +289,8 @@ class MultiperspectivePerceptron : public BPredUnit
     static int xlat4[];
 
     /** History data is kept for each thread */
-    struct ThreadData {
+    struct ThreadData
+    {
         ThreadData(int num_filter, int n_local_histories,
             int local_history_length, int assoc,
             const std::vector<std::vector<int>> &blurrypath_bits,

src/cpu/pred/multiperspective_perceptron_tage.hh

@@ -52,7 +52,8 @@ class MPP_TAGE : public TAGEBase
 {
     std::vector<unsigned int> tunedHistoryLengths;
   public:
-    struct BranchInfo : public TAGEBase::BranchInfo {
+    struct BranchInfo : public TAGEBase::BranchInfo
+    {
         BranchInfo(TAGEBase &tage) : TAGEBase::BranchInfo(tage)
         {}
         virtual ~BranchInfo()
@@ -145,7 +146,8 @@ class MPP_StatisticalCorrector : public StatisticalCorrector
     };
 
   public:
-    struct BranchInfo : public StatisticalCorrector::BranchInfo {
+    struct BranchInfo : public StatisticalCorrector::BranchInfo
+    {
         virtual ~BranchInfo()
         {}
     };

src/cpu/pred/simple_indirect.hh

@@ -87,7 +87,8 @@ class SimpleIndirectPredictor : public IndirectPredictor
     };
 
 
-    struct ThreadInfo {
+    struct ThreadInfo
+    {
         ThreadInfo() : headHistEntry(0), ghr(0) { }
 
         std::deque<HistoryEntry> pathHist;

src/cpu/pred/statistical_corrector.hh

@@ -66,7 +66,8 @@ class StatisticalCorrector : public SimObject
         }
     }
     // histories used for the statistical corrector
-    struct SCThreadHistory {
+    struct SCThreadHistory
+    {
         SCThreadHistory() {
             bwHist = 0;
             numOrdinalHistories = 0;
@@ -182,7 +183,8 @@ class StatisticalCorrector : public SimObject
     int8_t firstH;
     int8_t secondH;
 
-    struct StatisticalCorrectorStats : public Stats::Group {
+    struct StatisticalCorrectorStats : public Stats::Group
+    {
         StatisticalCorrectorStats(Stats::Group *parent);
         Stats::Scalar correct;
         Stats::Scalar wrong;

src/cpu/pred/tage.hh

@@ -60,7 +60,8 @@ class TAGE: public BPredUnit
   protected:
     TAGEBase *tage;
 
-    struct TageBranchInfo {
+    struct TageBranchInfo
+    {
         TAGEBase::BranchInfo *tageBranchInfo;
 
         TageBranchInfo(TAGEBase &tage) : tageBranchInfo(tage.makeBranchInfo())

src/cpu/pred/tage_base.hh

@@ -431,7 +431,8 @@ class TAGEBase : public SimObject
 
     // Keep per-thread histories to
     // support SMT.
-    struct ThreadHistory {
+    struct ThreadHistory
+    {
         // Speculative path history
         // (LSB of branch address)
         int pathHist;
@@ -482,7 +483,8 @@ class TAGEBase : public SimObject
 
     bool initialized;
 
-    struct TAGEBaseStats : public Stats::Group {
+    struct TAGEBaseStats : public Stats::Group
+    {
         TAGEBaseStats(Stats::Group *parent, unsigned nHistoryTables);
         // stats
         Stats::Scalar longestMatchProviderCorrect;

src/cpu/pred/tage_sc_l.hh

@@ -63,7 +63,8 @@ class TAGE_SC_L_TAGE : public TAGEBase
     const bool truncatePathHist;
 
   public:
-    struct BranchInfo : public TAGEBase::BranchInfo {
+    struct BranchInfo : public TAGEBase::BranchInfo
+    {
         bool lowConf;
         bool highConf;
         bool altConf;

src/cpu/pred/tournament.hh

@@ -151,7 +151,8 @@ class TournamentBP : public BPredUnit
      * when the BP can use this information to update/restore its
      * state properly.
      */
-    struct BPHistory {
+    struct BPHistory
+    {
 #ifdef DEBUG
         BPHistory()
         { newCount++; }

src/cpu/simple/probes/simpoint.hh

@@ -98,7 +98,8 @@ class SimPoint : public ProbeListenerObject
     OutputStream *simpointStream;
 
     /** Basic Block information */
-    struct BBInfo {
+    struct BBInfo
+    {
         /** Unique ID */
         uint64_t id;
         /** Num of static insts in BB */

src/cpu/simple/timing.hh

@@ -329,7 +329,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     EventFunctionWrapper fetchEvent;
 
-    struct IprEvent : Event {
+    struct IprEvent : Event
+    {
         Packet *pkt;
         TimingSimpleCPU *cpu;
         IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);

src/cpu/testers/traffic_gen/base.hh

@@ -191,7 +191,8 @@ class BaseTrafficGen : public ClockedObject
     /** Reqs waiting for response **/
     std::unordered_map<RequestPtr,Tick> waitingResp;
 
-    struct StatGroup : public Stats::Group {
+    struct StatGroup : public Stats::Group
+    {
         StatGroup(Stats::Group *parent);
 
         /** Count the number of dropped requests. */

src/cpu/testers/traffic_gen/trace_gen.hh

@@ -63,7 +63,8 @@ class TraceGen : public BaseGen
     /**
      * This struct stores a line in the trace file.
      */
-    struct TraceElement {
+    struct TraceElement
+    {
 
         /** Specifies if the request is to be a read or a write */
         MemCmd cmd;

src/cpu/testers/traffic_gen/traffic_gen.hh

@@ -100,7 +100,8 @@ class TrafficGen : public BaseTrafficGen
     size_t nextState();
 
     /** Struct to represent a probabilistic transition during parsing. */
-    struct Transition {
+    struct Transition
+    {
         uint32_t from;
         uint32_t to;
         double p;

src/cpu/thread_state.hh

@@ -43,7 +43,8 @@ class Checkpoint;
  *  memory, quiesce events, and certain stats.  This can be expanded
  *  to hold more thread-specific stats within it.
  */
-struct ThreadState : public Serializable {
+struct ThreadState : public Serializable
+{
     typedef ThreadContext::Status Status;
 
     ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);