stdlib: fix HBM2Stack component get_mem_port

This change makes sure that the ruby directory controllers
see the entire address range covered by a single HBMCtrl
(including two pseudo channels/dram interfaces)

Change-Id: I89d01d7bc78e98ee0ef6113dc0c97de6acf2e256
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62873
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/python/gem5/components/memory/hbm.py

@@ -32,7 +32,7 @@ from .abstract_memory_system import AbstractMemorySystem
 from math import log
 from ...utils.override import overrides
 from m5.objects import AddrRange, DRAMInterface, HBMCtrl, Port
-from typing import Type, Optional, Union
+from typing import Type, Optional, Union, Sequence, Tuple
 from .memory import _try_convert
 from .dram_interfaces.hbm import HBM_2000_4H_1x64
 
@@ -136,6 +136,28 @@ class HighBandwidthMemory(ChanneledMemory):
                 intlvMatch=(i << 1) | 1,
             )
 
+    @overrides(ChanneledMemory)
+    def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+
+        intlv_bits = log(self._num_channels, 2)
+        mask_list = []
+
+        for ib in range(int(intlv_bits)):
+            mask_list.append(1 << int(ib + log(self._intlv_size, 2)))
+        addr_ranges = []
+        for i in range(len(self.mem_ctrl)):
+            addr_ranges.append(
+                AddrRange(
+                    start=self._mem_range.start,
+                    size=self._mem_range.size(),
+                    masks=mask_list,
+                    intlvMatch=i,
+                )
+            )
+        return [
+            (addr_ranges[i], ctrl.port) for i, ctrl in enumerate(self.mem_ctrl)
+        ]
+
 
 def HBM2Stack(
     size: Optional[str] = "4GiB",