diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 8ce0a5219f..c7d46ff6b1 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -366,8 +366,8 @@ class FastModelCortexA76Cluster(SimObject):
 
 class FastModelScxEvsCortexA76x1(SystemC_ScModule):
     type = 'FastModelScxEvsCortexA76x1'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x1Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexA76<' \
+                    'gem5::fastmodel::ScxEvsCortexA76x1Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
 
@@ -378,8 +378,8 @@ class FastModelCortexA76x1(FastModelCortexA76Cluster):
 
 class FastModelScxEvsCortexA76x2(SystemC_ScModule):
     type = 'FastModelScxEvsCortexA76x2'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x2Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexA76<' \
+                    'gem5::fastmodel::ScxEvsCortexA76x2Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
 
@@ -391,8 +391,8 @@ class FastModelCortexA76x2(FastModelCortexA76Cluster):
 
 class FastModelScxEvsCortexA76x3(SystemC_ScModule):
     type = 'FastModelScxEvsCortexA76x3'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x3Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexA76<' \
+                    'gem5::fastmodel::ScxEvsCortexA76x3Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
 
@@ -405,8 +405,8 @@ class FastModelCortexA76x3(FastModelCortexA76Cluster):
 
 class FastModelScxEvsCortexA76x4(SystemC_ScModule):
     type = 'FastModelScxEvsCortexA76x4'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x4Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexA76<' \
+                    'gem5::fastmodel::ScxEvsCortexA76x4Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
 
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 7c8a0fafb5..9404edf1dc 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -171,8 +171,8 @@ class FastModelCortexR52Cluster(SimObject):
 
 class FastModelScxEvsCortexR52x1(SystemC_ScModule):
     type = 'FastModelScxEvsCortexR52x1'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x1Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexR52<' \
+                    'gem5::fastmodel::ScxEvsCortexR52x1Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
 
@@ -183,8 +183,8 @@ class FastModelCortexR52x1(FastModelCortexR52Cluster):
 
 class FastModelScxEvsCortexR52x2(SystemC_ScModule):
     type = 'FastModelScxEvsCortexR52x2'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x2Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexR52<' \
+                    'gem5::fastmodel::ScxEvsCortexR52x2Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
 
@@ -196,8 +196,8 @@ class FastModelCortexR52x2(FastModelCortexR52Cluster):
 
 class FastModelScxEvsCortexR52x3(SystemC_ScModule):
     type = 'FastModelScxEvsCortexR52x3'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x3Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexR52<' \
+                    'gem5::fastmodel::ScxEvsCortexR52x3Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
 
@@ -210,8 +210,8 @@ class FastModelCortexR52x3(FastModelCortexR52Cluster):
 
 class FastModelScxEvsCortexR52x4(SystemC_ScModule):
     type = 'FastModelScxEvsCortexR52x4'
-    cxx_class = \
-        'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x4Types>'
+    cxx_class = 'gem5::fastmodel::ScxEvsCortexR52<' \
+                    'gem5::fastmodel::ScxEvsCortexR52x4Types>'
     cxx_template_params = [ 'class Types' ]
     cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
 
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
index 6fe843d194..dc3f9ec1bf 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -223,7 +223,7 @@ PL330::allocateIrq(int idx, int count)
     }
 }
 
-::Port &
+gem5::Port &
 PL330::gem5_getPort(const std::string &if_name, int idx)
 {
     if (if_name == "dma") {
diff --git a/src/arch/arm/fastmodel/protocol/ExportedClockRateControlProtocol.lisa b/src/arch/arm/fastmodel/protocol/ExportedClockRateControlProtocol.lisa
index 03195846ab..093c5445fe 100644
--- a/src/arch/arm/fastmodel/protocol/ExportedClockRateControlProtocol.lisa
+++ b/src/arch/arm/fastmodel/protocol/ExportedClockRateControlProtocol.lisa
@@ -36,8 +36,8 @@ protocol ExportedClockRateControl
         description = "Exportable version of the clock rate control protocol.";
         version = "1.0";
         dso_safe = 0;
-        sc_slave_base_class_name = "ClockRateControlSlaveBase";
-        sc_slave_socket_class_name = "ClockRateControlTargetSocket";
+        sc_slave_base_class_name = "gem5::ClockRateControlSlaveBase";
+        sc_slave_socket_class_name = "gem5::ClockRateControlTargetSocket";
     }
 
     slave behavior set_mul_div(uint64_t mul, uint64_t div);
diff --git a/src/arch/arm/fastmodel/protocol/SignalInterruptProtocol.lisa b/src/arch/arm/fastmodel/protocol/SignalInterruptProtocol.lisa
index 4665e0b674..6f941be831 100644
--- a/src/arch/arm/fastmodel/protocol/SignalInterruptProtocol.lisa
+++ b/src/arch/arm/fastmodel/protocol/SignalInterruptProtocol.lisa
@@ -36,8 +36,8 @@ protocol SignalInterrupt
         description = "Signal an interrupt from gem5.";
         version = "1.0";
         dso_safe = 0;
-        sc_slave_base_class_name = "SignalInterruptSlaveBase";
-        sc_slave_socket_class_name = "SignalInterruptTargetSocket";
+        sc_slave_base_class_name = "gem5::SignalInterruptSlaveBase";
+        sc_slave_socket_class_name = "gem5::SignalInterruptTargetSocket";
     }
 
     slave behavior ppi(uint8_t cpu, uint32_t num, bool state);