diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 5240eb2a9c..0dfe3ecf1c 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -53,7 +53,6 @@ class ThreadContext;
 namespace MipsISA {
 
 // WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-// We just need this to make compiler happy. Use "PTE" type for real entry.
 struct TlbEntry
 {
     Addr _pageStart;