cpu: Switch off of the CPU's comInstEventQueue.
This switches to letting the ThreadContexts use a thread based/local comInstEventQueue instead of falling back to the CPU's array. Because the implementation is no longer shared and it's not given where the comInstEventQueue (or other implementation) should be accessed, the default implementation has been removed. Also, because nobody is using the CPU's array of event queues, those have been removed. Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -77,8 +77,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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Process *_process, BaseTLB *_itb,
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BaseTLB *_dtb, TheISA::ISA *_isa)
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: ThreadState(_cpu, _thread_num, _process), isa(_isa),
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predicate(true), memAccPredicate(true), system(_sys),
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itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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predicate(true), memAccPredicate(true),
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comInstEventQueue("instruction-based event queue"),
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system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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{
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clearArchRegs();
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quiesceEvent = new EndQuiesceEvent(this);
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@@ -88,8 +89,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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BaseTLB *_itb, BaseTLB *_dtb,
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TheISA::ISA *_isa, bool use_kernel_stats)
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: ThreadState(_cpu, _thread_num, NULL), isa(_isa),
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predicate(true), memAccPredicate(true), system(_sys),
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itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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predicate(true), memAccPredicate(true),
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comInstEventQueue("instruction-based event queue"),
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system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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{
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quiesceEvent = new EndQuiesceEvent(this);
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