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arch,cpu: Turn the Decoder objects into SimObjects.

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Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-25 04:08:04 -07:00
parent 3e766837b0
commit 25d36c81c9
30 changed files with 282 additions and 33 deletions
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12
src/cpu/BaseCPU.py
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@@ -60,26 +60,32 @@ if buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcMMU import SparcMMU as ArchMMU
from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA
from m5.objects.SparcDecoder import SparcDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'x86':
from m5.objects.X86MMU import X86MMU as ArchMMU
from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
from m5.objects.X86ISA import X86ISA as ArchISA
from m5.objects.X86Decoder import X86Decoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsMMU import MipsMMU as ArchMMU
from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
from m5.objects.MipsISA import MipsISA as ArchISA
from m5.objects.MipsDecoder import MipsDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'arm':
from m5.objects.ArmMMU import ArmMMU as ArchMMU
from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
from m5.objects.ArmISA import ArmISA as ArchISA
from m5.objects.ArmDecoder import ArmDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'power':
from m5.objects.PowerMMU import PowerMMU as ArchMMU
from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
from m5.objects.PowerISA import PowerISA as ArchISA
from m5.objects.PowerDecoder import PowerDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'riscv':
from m5.objects.RiscvMMU import RiscvMMU as ArchMMU
from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
from m5.objects.RiscvISA import RiscvISA as ArchISA
from m5.objects.RiscvDecoder import RiscvDecoder as ArchDecoder
else:
print("Don't know what object types to use for ISA %s" %
buildEnv['TARGET_ISA'])
@@ -152,6 +158,7 @@ class BaseCPU(ClockedObject):
mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
isa = VectorParam.BaseISA([], "ISA instance")
decoder = VectorParam.InstDecoder([], "Decoder instance")
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
@@ -231,11 +238,14 @@ class BaseCPU(ClockedObject):
# If no ISAs have been created, assume that the user wants the
# default ISA.
if len(self.isa) == 0:
self.isa = [ ArchISA() for i in range(self.numThreads) ]
self.isa = list([ ArchISA() for i in range(self.numThreads) ])
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError("Number of ISA instances doesn't "
"match thread count")
if len(self.decoder) != 0:
raise RuntimeError("Decoders should not be set up manually")
self.decoder = list([ ArchDecoder(isa=isa) for isa in self.isa ])
if self.checker != NULL:
self.checker.createThreads()