arch,cpu: Turn the Decoder objects into SimObjects.

Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/generic/SConscript

@@ -45,6 +45,7 @@ SimObject('BaseInterrupts.py')
 SimObject('BaseISA.py')
 SimObject('BaseMMU.py')
 SimObject('BaseTLB.py')
+SimObject('InstDecoder.py')
 
 DebugFlag('PageTableWalker',
           "Page table walker state machine debugging")
@@ -53,7 +54,4 @@ DebugFlag('TLB')
 GTest('vec_reg.test', 'vec_reg.test.cc')
 GTest('vec_pred_reg.test', 'vec_pred_reg.test.cc')
 
-if env['TARGET_ISA'] == 'null':
-    Return()
-
 Source('decoder.cc')