From 2579bacf06eb57b75b7fae1c9b1b133fa64f9841 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Sat, 13 May 2023 23:09:48 +0800
Subject: [PATCH] arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8

Remove unessential postfix like '_32' and '_64' from mnemonic

Change-Id: I83d47eeccd04fe61ac8ee0addd7221abbdcefbd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70600
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
---
 src/arch/riscv/isa/decoder.isa | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index ae2f0a4f55..c7eefbc79c 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1124,14 +1124,13 @@ decode QUADRANT default Unknown::unknown() {
                     0x10: sh1add({{
                         Rd = rvSext((Rs1 << 1) + Rs2);
                     }});
-                    0x14: decode RVTYPE {
-                        0x0: xperm4_32({{
-                            Rd_sw = _rvk_emu_xperm4_32(Rs1_sw, Rs2_sw);
-                        }});
-                        0x1: xperm4_64({{
+                    0x14: xperm4({{
+                        if (machInst.rv_type == RV32) {
+                            Rd_sd = _rvk_emu_xperm4_32(Rs1_sd, Rs2_sd);
+                        } else {
                             Rd_sd = _rvk_emu_xperm4_64(Rs1_sd, Rs2_sd);
-                        }});
-                    }
+                        }
+                    }});
                 }
                 0x3: decode FUNCT7 {
                     0x0: sltu({{
@@ -1181,14 +1180,13 @@ decode QUADRANT default Unknown::unknown() {
                     0x10: sh2add({{
                         Rd = rvSext((Rs1 << 2) + Rs2);
                     }});
-                    0x14: decode RVTYPE {
-                        0x0: xperm8_32({{
-                            Rd_sw = _rvk_emu_xperm8_32(Rs1_sw, Rs2_sw);
-                        }});
-                        0x1: xperm8_64({{
+                    0x14: xperm8({{
+                        if (machInst.rv_type == RV32) {
+                            Rd_sd = _rvk_emu_xperm8_32(Rs1_sd, Rs2_sd);
+                        } else {
                             Rd_sd = _rvk_emu_xperm8_64(Rs1_sd, Rs2_sd);
-                        }});
-                    }
+                        }
+                    }});
                     0x20: xnor({{
                         Rd = rvSext(~(Rs1 ^ Rs2));
                     }});