dev-arm: Implement a SMMUv3 model
This is an implementation of the SMMUv3 architecture. What can it do? - Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add. - Large pages are supported. - Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId What it can't do? - Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported - Invalidations take zero time. This wouldn't be hard to fix. - Checkpointing is not supported - Stall/resume for faulting transactions is not supported Additional contributors: - Michiel W. van Tol <Michiel.VanTol@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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committed by
Giacomo Travaglini
parent
f2be9f195c
commit
2574dc41a6
@@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'arm':
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SimObject('FlashDevice.py')
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SimObject('Gic.py')
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SimObject('RealView.py')
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SimObject('SMMUv3.py')
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SimObject('UFSHostDevice.py')
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SimObject('EnergyCtrl.py')
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SimObject('NoMali.py')
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@@ -66,6 +67,15 @@ if env['TARGET_ISA'] == 'arm':
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Source('pl111.cc')
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Source('hdlcd.cc')
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Source('kmi.cc')
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Source('smmu_v3.cc');
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Source('smmu_v3_caches.cc');
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Source('smmu_v3_cmdexec.cc');
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Source('smmu_v3_events.cc');
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Source('smmu_v3_ports.cc');
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Source('smmu_v3_proc.cc');
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Source('smmu_v3_ptops.cc');
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Source('smmu_v3_slaveifc.cc');
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Source('smmu_v3_transl.cc');
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Source('timer_sp804.cc')
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Source('gpu_nomali.cc')
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Source('pci_host.cc')
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@@ -88,6 +98,8 @@ if env['TARGET_ISA'] == 'arm':
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DebugFlag('GIC')
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DebugFlag('ITS')
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DebugFlag('RVCTRL')
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DebugFlag('SMMUv3')
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DebugFlag('SMMUv3Hazard')
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DebugFlag('EnergyCtrl')
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DebugFlag('UFSHostDevice')
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DebugFlag('VGIC')
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