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arch,cpu: Add vector predicate registers

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Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Giacomo Gabrielli
2018-10-16 16:04:08 +01:00
parent c6f5db8743
commit 25474167e5
50 changed files with 1370 additions and 101 deletions
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6
src/arch/SConscript
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@@ -1,6 +1,6 @@
# -*- mode:python -*-
# Copyright (c) 2016 ARM Limited
# Copyright (c) 2016-2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -226,6 +226,8 @@ Export('ISADesc')
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
DebugFlag('VecRegs')
DebugFlag('VecPredRegs')
DebugFlag('CCRegs')
DebugFlag('MiscRegs')
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs',
'CCRegs', 'MiscRegs' ])