From 24e2ef0b7808f971f3ea651d9946770b3a2a9055 Mon Sep 17 00:00:00 2001 From: Matt Sinclair Date: Sat, 7 Jan 2023 16:01:57 -0600 Subject: [PATCH] mem-ruby, gpu-compute: fix TCP GLC cache bypassing 66d4a158 added support for AMD's GPU cache bypassing flags (GLC for bypassing L1 caches, SLC for bypassing all caches). However, for applications that use the GLC flag but intermix GLC- and non-GLC accesses to the same address, this previous commit has a bug. This bug manifests when the address is currently valid in the L1 (TCP). In this case, the previous commit chose to evict the line before letting the bypassing access to proceed. However, to do this the previous commit was using the inv_invDone action as part of the process of evicting it. This action is only intended to be called when load acquires are being performed (i.e., when the entire L1 cache is being flash invalidated). Thus, calling inv_invDone for a GLC (or SLC) bypassing request caused an assert failure since the bypassing request was not performing a load acquire. This commit resolves this by changing the support in this case to simply invalidate the entry in the cache. Change-Id: Ibaa4976f8714ac93650020af1c0ce2b6732c95a2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67199 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- src/mem/ruby/protocol/GPU_VIPER-TCP.sm | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm index 3be1397d49..14bdcecbc2 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm @@ -614,7 +614,6 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)") // request to L2. transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} { uu_profileDataMiss; - inv_invDone; ic_invCache; n_issueRdBlk; p_popMandatoryQueue;