derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Remove readVecPredReg from ThreadContext::compare.

Browse Source 
Use the generic getReg method to avoid having to use the
TheISA::VecPredRegContainer type.

Change-Id: I8240dd85f2db2f8125d7944135c4361866fba057
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49700
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 03:40:48 -07:00
parent 973d9c82c0
commit 22eeeaff86
1 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/cpu/thread_context.cc
View File

@@ -41,6 +41,8 @@
#include "cpu/thread_context.hh"
#include <vector>
#include "arch/generic/vec_pred_reg.hh"
#include "base/logging.hh"
#include "base/trace.hh"
@@ -91,13 +93,19 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
}
// Then loop through the predicate registers.
for (int i = 0; i < regClasses.at(VecPredRegClass).numRegs(); ++i) {
const auto &vec_pred_class = regClasses.at(VecPredRegClass);
std::vector<uint8_t> pred1(vec_pred_class.regBytes());
std::vector<uint8_t> pred2(vec_pred_class.regBytes());
for (int i = 0; i < vec_pred_class.numRegs(); ++i) {
RegId rid(VecPredRegClass, i);
const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
if (t1 != t2)
panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
one->getReg(rid, pred1.data());
two->getReg(rid, pred2.data());
if (pred1 != pred2) {
panic("Pred reg idx %d doesn't match, one: %s, two: %s",
i, vec_pred_class.valString(pred1.data()),
vec_pred_class.valString(pred2.data()));
}
}
for (int i = 0; i < regClasses.at(MiscRegClass).numRegs(); ++i) {