From 2242196f03c6f73d62077b1437929eadee8e8741 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 13 Jul 2023 18:57:51 +0100
Subject: [PATCH] arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75)

When shiftAmt is 0 for a UQRSHL instruction, the code called bits() with
incorrect arguments. This fixes a left-shift of 0 to be a NOP/mov, as
required.

Change-Id: Ic86ca40ac42bfb767a09e8c65a53cec56382a008

Co-authored-by: Marton Erdos <marton.erdos@arm.com>
---
 src/arch/arm/isa/insts/neon64.isa | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index 6608f61688..a3b79be912 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -3403,7 +3403,7 @@ let {{
                     destElem = (srcElem1 >> shiftAmt);
                 }
                 destElem += rBit;
-            } else {
+            } else if (shiftAmt > 0) {
                 if (shiftAmt >= sizeof(Element) * 8) {
                     if (srcElem1 != 0) {
                         destElem = mask(sizeof(Element) * 8);
@@ -3421,6 +3421,8 @@ let {{
                         destElem = srcElem1 << shiftAmt;
                     }
                 }
+            } else {
+                destElem = srcElem1;
             }
             FpscrQc = fpscr;
     '''