diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py index 33b6940c3f..b4486b9350 100644 --- a/src/dev/riscv/Plic.py +++ b/src/dev/riscv/Plic.py @@ -1,4 +1,5 @@ # Copyright (c) 2021 Huawei International +# Copyright (c) 2023 Google LLC # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -39,7 +40,22 @@ from m5.proxy import * from m5.util.fdthelper import * -class Plic(BasicPioDevice): +class PlicBase(BasicPioDevice): + """ + This is abstract class of PLIC and + define interface to handle received + interrupt singal from device + """ + + type = "PlicBase" + cxx_header = "dev/riscv/plic.hh" + cxx_class = "gem5::PlicBase" + abstract = True + + pio_size = Param.Addr("PIO Size") + + +class Plic(PlicBase): """ This implementation of PLIC is based on the SiFive U54MC datasheet: @@ -51,7 +67,7 @@ class Plic(BasicPioDevice): type = "Plic" cxx_header = "dev/riscv/plic.hh" cxx_class = "gem5::Plic" - pio_size = Param.Addr(0x4000000, "PIO Size") + pio_size = 0x4000000 n_src = Param.Int("Number of interrupt sources") n_contexts = Param.Int( "Number of interrupt contexts. Usually the number " diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript index af0b96b88e..6e3376bb02 100755 --- a/src/dev/riscv/SConscript +++ b/src/dev/riscv/SConscript @@ -2,6 +2,7 @@ # Copyright (c) 2021 Huawei International # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS) +# Copyright (c) 2023 Google LLC # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +35,7 @@ SimObject('HiFive.py', sim_objects=['HiFive', 'GenericRiscvPciHost'], SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa') SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa') SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa') -SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa') +SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa') SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa') SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'], tags='riscv isa') diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc index 371af9e78a..fd42920dc5 100644 --- a/src/dev/riscv/plic.cc +++ b/src/dev/riscv/plic.cc @@ -45,6 +45,7 @@ #include "mem/packet.hh" #include "mem/packet_access.hh" #include "params/Plic.hh" +#include "params/PlicBase.hh" #include "sim/system.hh" namespace gem5 @@ -53,7 +54,7 @@ namespace gem5 using namespace RiscvISA; Plic::Plic(const Params ¶ms) : - BasicPioDevice(params, params.pio_size), + PlicBase(params), system(params.system), nSrc(params.n_src), nContext(params.n_contexts), diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh index d077e73617..00128ee56c 100644 --- a/src/dev/riscv/plic.hh +++ b/src/dev/riscv/plic.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Huawei International + * Copyright (c) 2023 Google LLC * All rights reserved * * The license below extends only to copyright in the software and shall @@ -47,6 +48,7 @@ #include "mem/packet.hh" #include "mem/packet_access.hh" #include "params/Plic.hh" +#include "params/PlicBase.hh" #include "sim/system.hh" namespace gem5 @@ -94,7 +96,21 @@ struct PlicOutput std::vector maxPriority; }; -class Plic : public BasicPioDevice +class PlicBase : public BasicPioDevice +{ + public: + typedef PlicBaseParams Params; + PlicBase(const Params ¶ms) : + BasicPioDevice(params, params.pio_size) + {} + + // Interrupt interface to send signal to PLIC + virtual void post(int src_id) = 0; + // Interrupt interface to clear signal to PLIC + virtual void clear(int src_id) = 0; +}; + +class Plic : public PlicBase { // Params protected: @@ -125,8 +141,8 @@ class Plic : public BasicPioDevice /** * Interrupt interface */ - void post(int src_id); - void clear(int src_id); + void post(int src_id) override; + void clear(int src_id) override; /** * SimObject functions