From 21f6e166b7f8fe9dcf9c23e4c890773ed6798a26 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Wed, 17 Jul 2024 14:57:52 -0700 Subject: [PATCH] arch-vega: Panic on SDWAB / DPP VOPC unimplemented If SDWAB or DPP are used on a VOPC instruction and those are not implemented, it is highly likely to be a problem for the application. Rather than continue to execute and cause undefined behavior, exit the simulation with a panic showing the line of the instruction causing the issue. Change-Id: Ib3f94df7445d068b26907470c1f733be16cd2fc2 --- src/arch/amdgpu/vega/insts/vopc.cc | 390 +++++++++++++++++++++++++++++ 1 file changed, 390 insertions(+) diff --git a/src/arch/amdgpu/vega/insts/vopc.cc b/src/arch/amdgpu/vega/insts/vopc.cc index 0e1fb04f75..9361e68b67 100644 --- a/src/arch/amdgpu/vega/insts/vopc.cc +++ b/src/arch/amdgpu/vega/insts/vopc.cc @@ -74,6 +74,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { if (bits(src1[lane], 0) || bits(src1[lane], 1)) { @@ -189,6 +192,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { if (bits(src1[lane], 0) || bits(src1[lane], 1)) { @@ -304,6 +310,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { if (bits(src1[lane], 0) || bits(src1[lane], 1)) { @@ -420,6 +429,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { if (bits(src1[lane], 0) || bits(src1[lane], 1)) { @@ -1277,6 +1289,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -1311,6 +1326,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -1345,6 +1363,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -1379,6 +1400,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -1413,6 +1437,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (src0[lane] < src1[lane] @@ -1448,6 +1475,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -1482,6 +1512,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (!std::isnan(src0[lane]) @@ -1517,6 +1550,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (std::isnan(src0[lane]) @@ -1552,6 +1588,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0); @@ -1586,6 +1625,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane] @@ -1621,6 +1663,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0); @@ -1655,6 +1700,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0); @@ -1689,6 +1737,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -1723,6 +1774,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0); @@ -1818,6 +1872,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -1854,6 +1911,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -1890,6 +1950,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -1926,6 +1989,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -1962,6 +2028,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (src0[lane] < src1[lane] @@ -1999,6 +2068,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -2036,6 +2108,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (!std::isnan(src0[lane]) @@ -2074,6 +2149,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (std::isnan(src0[lane]) @@ -2111,6 +2189,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0); @@ -2147,6 +2228,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane] @@ -2184,6 +2268,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0); @@ -2220,6 +2307,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0); @@ -2256,6 +2346,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] == src1[lane]) ? 1 : 0); @@ -2292,6 +2385,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0); @@ -2387,6 +2483,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -2421,6 +2520,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -2455,6 +2557,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -2489,6 +2594,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -2523,6 +2631,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (src0[lane] < src1[lane] @@ -2558,6 +2669,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -2592,6 +2706,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (!std::isnan(src0[lane]) @@ -2627,6 +2744,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (std::isnan(src0[lane]) @@ -2662,6 +2782,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0); @@ -2696,6 +2819,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane] @@ -2731,6 +2857,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0); @@ -2765,6 +2894,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0); @@ -2799,6 +2931,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -2833,6 +2968,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0); @@ -2928,6 +3066,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -2964,6 +3105,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -3000,6 +3144,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -3036,6 +3183,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -3072,6 +3222,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (src0[lane] < src1[lane] @@ -3109,6 +3262,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -3146,6 +3302,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (!std::isnan(src0[lane]) @@ -3184,6 +3343,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, (std::isnan(src0[lane]) @@ -3221,6 +3383,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0); @@ -3257,6 +3422,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane] @@ -3294,6 +3462,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0); @@ -3330,6 +3501,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0); @@ -3366,6 +3540,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -3402,6 +3579,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0); @@ -3495,6 +3675,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -3528,6 +3711,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -3561,6 +3747,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -3594,6 +3783,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -3627,6 +3819,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -3660,6 +3855,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -3749,6 +3947,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -3823,6 +4024,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -3856,6 +4060,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -3932,6 +4139,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -4024,6 +4234,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -4059,6 +4272,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -4094,6 +4310,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -4129,6 +4348,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -4164,6 +4386,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -4199,6 +4424,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -4294,6 +4522,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -4329,6 +4560,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -4364,6 +4598,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -4399,6 +4636,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -4434,6 +4674,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -4469,6 +4712,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -4561,6 +4807,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -4594,6 +4843,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -4627,6 +4879,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -4660,6 +4915,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -4693,6 +4951,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -4726,6 +4987,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -4815,6 +5079,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -4848,6 +5115,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -4881,6 +5151,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -4914,6 +5187,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -4947,6 +5223,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -4980,6 +5259,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -5072,6 +5354,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -5107,6 +5392,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -5142,6 +5430,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -5177,6 +5468,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -5212,6 +5506,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -5247,6 +5544,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -5342,6 +5642,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -5377,6 +5680,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -5412,6 +5718,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -5447,6 +5756,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -5482,6 +5794,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -5517,6 +5832,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -5609,6 +5927,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -5642,6 +5963,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -5675,6 +5999,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -5708,6 +6035,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -5741,6 +6071,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -5774,6 +6107,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -5863,6 +6199,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -5896,6 +6235,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -5929,6 +6271,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -5962,6 +6307,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -5995,6 +6343,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -6028,6 +6379,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -6120,6 +6474,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -6155,6 +6512,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -6190,6 +6550,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -6225,6 +6588,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -6260,6 +6626,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -6295,6 +6664,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0); @@ -6390,6 +6762,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0); @@ -6425,6 +6800,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0); @@ -6460,6 +6838,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0); @@ -6495,6 +6876,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0); @@ -6530,6 +6914,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0); @@ -6565,6 +6952,9 @@ namespace VegaISA src0.readSrc(); src1.read(); + panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode); + panic_if(isDPPInst(), "DPP not supported for %s", _opcode); + for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (wf->execMask(lane)) { vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);