From 218d6b239d60b649476dc8361687a6a9f30af09f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 21 Aug 2021 20:55:49 -0700 Subject: [PATCH] arch: Add some indirection for Operand RegId generation. That introduces a place to hook in to override what actual register index is passed to the rest of gem5. Change-Id: I77d778849410ee5d32bab669bba411e80603a002 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49739 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/isa_parser/operand_types.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py index ea2780eac0..4079bcdc89 100755 --- a/src/arch/isa_parser/operand_types.py +++ b/src/arch/isa_parser/operand_types.py @@ -100,8 +100,8 @@ class Operand(object): derived classes encapsulates the traits of a particular operand type (e.g., "32-bit integer register").''' - src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));' - dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));' + src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, %s);' + dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, %s);' def buildReadCode(self, pred_read, op_idx): subst_dict = {"name": self.base_name, @@ -125,6 +125,9 @@ class Operand(object): if (traceData) {{ traceData->setData(final_val); }} }}''' + def regId(self): + return f'RegId({self.reg_class}, {self.reg_spec})' + def __init__(self, parser, full_name, ext, is_src, is_dest): self.parser = parser self.full_name = full_name @@ -220,13 +223,13 @@ class RegOperand(Operand): c_dest = '' if self.is_src: - c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec) + c_src = self.src_reg_constructor % self.regId() if self.hasReadPred(): c_src = '\n\tif (%s) {%s\n\t}' % \ (self.read_predicate, c_src) if self.is_dest: - c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec) + c_dest = self.dst_reg_constructor % self.regId() c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;' if self.hasWritePred(): c_dest = '\n\tif (%s) {%s\n\t}' % \ @@ -481,10 +484,10 @@ class ControlRegOperand(Operand): c_dest = '' if self.is_src: - c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec) + c_src = self.src_reg_constructor % self.regId() if self.is_dest: - c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec) + c_dest = self.dst_reg_constructor % self.regId() return c_src + c_dest