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inorder/alpha-isa: create eaComp object visible to StaticInst through ISA

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Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
This commit is contained in:
Korey Sewell
2009-05-12 15:01:14 -04:00
parent b569f8f0ed
commit 2012202b06
5 changed files with 36 additions and 218 deletions
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4
src/cpu/SConscript
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@@ -49,6 +49,8 @@ execfile(models_db.srcnode().abspath)
# Template for execute() signature.
exec_sig_template = '''
virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
@@ -59,6 +61,8 @@ virtual int memAccSize(%(type)s *xc)
'''
mem_ini_sig_template = '''
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''