From 1fd8fa90757a035885d51861c5e64d9f6cecb8bc Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 17:17:57 +0530
Subject: [PATCH] arch-power: Add word divide-extended instructions

This adds the following instructions.
  * Divide Word Extended (divwe[o][.])
  * Divide Word Extended Unsigned (divweu[o][.])

Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40906
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/power/isa/decoder.isa | 36 ++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e8fcb6676b..258a696106 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -574,6 +574,42 @@ decode PO default Unknown::unknown() {
             266: IntSumOp::add({{ Ra }}, {{ Rb }});
 
             format IntArithCheckRcOp {
+                395: divweu({{
+                    uint32_t src1 = Ra_ud;
+                    uint32_t src2 = Rb_ud;
+                    uint64_t res;
+                    if (src2 != 0) {
+                        res = ((uint64_t)src1 << 32) / src2;
+                        if (res <= UINT32_MAX) {
+                            Rt = (uint32_t)res;
+                        } else {
+                            Rt = 0;
+                            setOV = true;
+                        }
+                    } else {
+                        Rt = 0;
+                        setOV = true;
+                    }
+                }}, true);
+
+                427: divwe({{
+                    int32_t src1 = Ra_sw;
+                    int32_t src2 = Rb_sw;
+                    int64_t res;
+                    if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+                        res = ((int64_t)src1 << 32) / src2;
+                        if (res == (int32_t)res) {
+                            Rt = (uint32_t)res;
+                        } else {
+                            Rt = 0;
+                            setOV = true;
+                        }
+                    } else {
+                        Rt = 0;
+                        setOV = true;
+                    }
+                }}, true);
+
                 459: divwu({{
                     uint32_t src1 = Ra_uw;
                     uint32_t src2 = Rb_uw;