mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
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@@ -1870,7 +1870,7 @@ class SlavePort(Port):
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raise TypeError, 'wrong number of arguments'
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# VectorPort description object. Like Port, but represents a vector
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# of connections (e.g., as on a Bus).
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# of connections (e.g., as on a XBar).
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class VectorPort(Port):
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def __init__(self, *args):
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self.isVec = True
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@@ -173,7 +173,7 @@ def dot_create_node(simNode, full_path, label):
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class NodeType:
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SYS = 0
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CPU = 1
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BUS = 2
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XBAR = 2
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MEM = 3
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DEV = 4
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OTHER = 5
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@@ -190,8 +190,8 @@ def get_node_type(simNode):
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elif 'PioDevice' in dir(m5.objects) and \
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isinstance(simNode, m5.objects.PioDevice):
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return NodeType.DEV
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elif isinstance(simNode, m5.objects.BaseBus):
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return NodeType.BUS
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elif isinstance(simNode, m5.objects.BaseXBar):
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return NodeType.XBAR
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elif isinstance(simNode, m5.objects.AbstractMemory):
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return NodeType.MEM
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else:
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@@ -205,7 +205,7 @@ def get_type_colour(nodeType):
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return (228, 231, 235)
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elif nodeType == NodeType.CPU:
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return (187, 198, 217)
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elif nodeType == NodeType.BUS:
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elif nodeType == NodeType.XBAR:
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return (111, 121, 140)
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elif nodeType == NodeType.MEM:
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return (94, 89, 88)
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