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mem-ruby: fix TCP spacing/spelling

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Change-Id: I3fd9009592c8716a3da19dcdccf68f16af6522ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67200
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matt Sinclair
2023-01-07 16:43:20 -06:00
committed by Matt Sinclair
parent 24e2ef0b78
commit 1d467bed7f
1 changed files with 6 additions and 6 deletions
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12
src/mem/ruby/protocol/GPU_VIPER-TCP.sm
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@@ -261,7 +261,7 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
// If L1 is disabled or requests have GLC or SLC flag set,
// then, the requests should not cache in the L1. The response
// from L2/global memory should bypass the cache
trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
@@ -288,7 +288,7 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
DPRINTF(RubySlicc, "%s\n", in_msg);
if (in_msg.Type == RubyRequestType:LD) {
if ((in_msg.isGLCSet || in_msg.isSLCSet) && is_valid(cache_entry)) {
// Read rquests with GLC or SLC bit set should not cache in the L1.
// Read requests with GLC or SLC bit set should not cache in the L1.
// They need to bypass the L1 and go to the L2. If an entry exists
// in the L1, it needs to be evicted
trigger(Event:LoadBypassEvict, in_msg.LineAddress, cache_entry, tbe);
@@ -609,15 +609,15 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
p_popMandatoryQueue;
}
// Transition to be called when a load request with GLC or SLC flag set arrives
// at L1. This transition invalidates any existing entry and forwards the
// request to L2.
// Transition to be called when a load request with GLC or SLC flag set arrives
// at L1. This transition invalidates any existing entry and forwards the
// request to L2.
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
uu_profileDataMiss;
ic_invCache;
n_issueRdBlk;
p_popMandatoryQueue;
}
}
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;